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sbcx-x s/t bus interface circuit extended peb/pef 3081 version 1.3 data sheet, ds 1, sept. 2000 wired communications never stop thinking.
edition 2000-09-27 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 9/28/00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
sbcx-x s/t bus interface circuit extended peb/pef 3081 version 1.3 p r el i m i nar y wired communications data sheet, ds 1, sept. 2000 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 3081 preliminary revision history: 2000-09-27 ds 1 previous version: page subjects (major changes since last revision)
peb 3081 pef 3081 table of contents page data sheet 5 2000-09-27 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 description of functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.2 programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.4 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.5 timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.6 activation indication via pin acl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 s/t-interface coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.2 s/t-interface multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.3 data transfer and delay between iom-2 and s/t . . . . . . . . . . . . . . . . 44 3.3.4 transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.5 receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.6 s/t interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.6.1 external protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.7 s/t interface delay compensation (te/lt-t mode) . . . . . . . . . . . . . . . 51 3.3.8 level detection power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.9 transceiver enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.10 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.1 description of the receive pll (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4.2 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4.3 oscillator clock output c768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5 control of layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.1 state machine te and lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.1.1 state transition diagram (te, lt-t) . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.1.2 states (te, lt-t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.5.1.3 c/i codes (te, lt-t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5.1.4 infos on s/t (te, lt-t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.5.2 state machine lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5.2.1 state transition diagram (lt-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5.2.2 states (lt-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.5.2.3 c/i codes (lt-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.5.2.4 infos on s/t (lt-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
peb 3081 pef 3081 table of contents page data sheet 6 2000-09-27 3.5.3 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.3.1 state transition diagram (nt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.3.2 states (nt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.5.3.3 c/i codes (nt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.4 command / indicate channel codes (c/i0) - overview . . . . . . . . . . . . . 78 3.6 control procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.6.1 example of activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.6.2 activation initiated by the terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.6.3 activation initiated by the network termination nt . . . . . . . . . . . . . . . . 81 3.7 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.7.1 iom-2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.7.1.1 controller data access (cda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.2 serial data strobe signal and strobed data clock . . . . . . . . . . . . . . . 96 3.7.2.1 serial data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.7.2.2 strobed iom-2 bit clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.7.3 iom-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.7.3.1 handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.7.3.2 error treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.7.3.3 monitor channel programming as a master device . . . . . . . . . . 105 3.7.3.4 monitor channel programming as a slave device . . . . . . . . . . . 106 3.7.3.5 monitor time-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.7.3.6 monitor interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.7.4 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.7.5 d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.7.5.1 tic bus d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . 111 3.7.5.2 s-bus priority mechanism for d-channel . . . . . . . . . . . . . . . . . . . . 113 3.7.5.3 s-bus d-channel control in lt-t . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.7.5.4 d-channel control in the intelligent nt (tic- and s-bus) . . . . . . . . 115 3.7.6 activation/deactivation of iom-2 interface . . . . . . . . . . . . . . . . . . . . . 119 3.8 auxiliary interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.1 transceiver and c/i registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.1 tr_mode2 - transceiver mode register 2 . . . . . . . . . . . . . . . . . . . . 132 4.1.2 cir0 - command/indication receive 0 . . . . . . . . . . . . . . . . . . . . . . . 133 4.1.3 cix0 - command/indication transmit 0 . . . . . . . . . . . . . . . . . . . . . . . 134 4.1.4 cir1 - command/indication receive 1 . . . . . . . . . . . . . . . . . . . . . . . 134 4.1.5 cix1 - command/indication transmit 1 . . . . . . . . . . . . . . . . . . . . . . . 135 4.1.6 tr_conf0 - transceiver configuration register 0 . . . . . . . . . . . . . . 135 4.1.7 tr_conf1 - transceiver configuration register 1 . . . . . . . . . . . . . . 137 4.1.8 tr_conf2 - transmitter configuration register 2 . . . . . . . . . . . . . . 137 4.1.9 tr_sta - transceiver status register . . . . . . . . . . . . . . . . . . . . . . . 139 4.1.10 tr_cmd - transceiver command register . . . . . . . . . . . . . . . . . . . . 140
peb 3081 pef 3081 table of contents page data sheet 7 2000-09-27 4.1.11 sqrr1 - s/q-channel receive register 1 . . . . . . . . . . . . . . . . . . . . 141 4.1.12 sqxr1- s/q-channel tx register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.1.13 sqrr2 - s/q-channel receive register 2 . . . . . . . . . . . . . . . . . . . . . 142 4.1.14 sqxr2 - s/q-channel tx register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.1.15 sqrr3 - s/q-channel receive register 3 . . . . . . . . . . . . . . . . . . . . 143 4.1.16 sqxr3 - s/q-channel tx register 3 . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.1.17 istatr - interrupt status register transceiver . . . . . . . . . . . . . . . . . 144 4.1.18 masktr - mask transceiver interrupt . . . . . . . . . . . . . . . . . . . . . . . . 145 4.1.19 tr_mode - transceiver mode register 1 . . . . . . . . . . . . . . . . . . . . . 145 4.2 auxiliary interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.2.1 acfg1 - auxiliary configuration register 1 . . . . . . . . . . . . . . . . . . . . 147 4.2.2 acfg2 - auxiliary configuration register 2 . . . . . . . . . . . . . . . . . . . . 147 4.2.3 aoe - auxiliary output enable register . . . . . . . . . . . . . . . . . . . . . . . 148 4.2.4 arx - auxiliary interface receive register . . . . . . . . . . . . . . . . . . . . 148 4.2.5 atx - auxiliary interface transmit register . . . . . . . . . . . . . . . . . . . . 149 4.3 iom-2 and monitor handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.3.1 cdaxy - controller data access register xy . . . . . . . . . . . . . . . . . . . 150 4.3.2 xxx_tsdpxy - time slot and data port selection for chxy . . . . . . . 151 4.3.3 cdax_cr - control register controller data access ch1x . . . . . . . 152 4.3.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) . . . 153 4.3.5 trc_cr - control register transceiver c/i0 (iom_cr.ci_cs=1) . . . 154 4.3.6 dci_cr - control register for ci1 handler (iom_cr.ci_cs=0) . . . . 154 4.3.7 dcic_cr - control register for ci0 handler (iom_cr.ci_cs=1) . . . 155 4.3.8 mon_cr - control register monitor data . . . . . . . . . . . . . . . . . . . . . 156 4.3.9 sdsx_cr - control register serial data strobe x . . . . . . . . . . . . . . . 157 4.3.10 iom_cr - control register iom data . . . . . . . . . . . . . . . . . . . . . . . . 158 4.3.11 sti - synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.3.12 asti - acknowledge synchronous transfer interrupt . . . . . . . . . . . . 161 4.3.13 msti - mask synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . 161 4.3.14 sds_conf - configuration register for serial data strobes . . . . . . 162 4.3.15 mcda - monitoring cda bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.3.16 mor - monitor receive channel . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.3.17 mox - monitor transmit channel . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.3.18 mosr - monitor interrupt status register . . . . . . . . . . . . . . . . . . . 164 4.3.19 mocr - monitor control register . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.3.20 msta - monitor status register . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.3.21 mconf - monitor configuration register . . . . . . . . . . . . . . . . . . . 165 4.4 interrupt and general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.4.1 ista - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.4.2 mask - mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.4.3 auxi - auxiliary interrupt status register . . . . . . . . . . . . . . . . . . . . . . 167 4.4.4 auxm - auxiliary mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
peb 3081 pef 3081 table of contents page data sheet 8 2000-09-27 4.4.5 mode1 - mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.4.6 mode2 - mode2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 4.4.7 id - identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.4.8 sres - software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.4.9 timr - timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.4 oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.6 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.7 serial control interface (sci) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.9 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.10 recommended transformer specification . . . . . . . . . . . . . . . . . . . . . . . 184 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
peb 3081 pef 3081 list of figures page data sheet 9 2000-09-27 figure 1 logic symbol of the sbcx-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2 applications of the sbcx-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3 pin configuration of the sbcx-x (p-mqfp-44) . . . . . . . . . . . . . . . . . 19 figure 4 pin configuration of the sbcx-x (p-tqfp-48) . . . . . . . . . . . . . . . . . . 20 figure 5 functional block diagram of the sbcx-x . . . . . . . . . . . . . . . . . . . . . . 26 figure 6 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8 interrupt status and mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10 timer interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11 timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12 acl indication of activated layer 1 on te side. . . . . . . . . . . . . . . . . . 37 figure 13 acl configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14 wiring configurations in user premises . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15 s/t-interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16 frame structure at reference points s and t (itu i.430). . . . . . . . . . 41 figure 17 data delay between iom-2 and s/t interface (te mode only) . . . . . . 44 figure 18 data delay between iom-2 and s/t interface with s/g bit evaluation (te mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19 data delay between iom-2 and s/t interface with 8 iom channels (lt-s/ nt mode only) 46 figure 20 data delay between iom-2 and s/t interface with 3 iom channels and maximum receive delay (lt-s/nt mode only). . . . . . . . . . . . . . . . . . 46 figure 21 equivalent internal circuit of the transmitter stage . . . . . . . . . . . . . . 47 figure 22 equivalent internal circuit of the receiver stage . . . . . . . . . . . . . . . . 48 figure 23 connection of line transformers and power supply to the sbcx-x . 49 figure 24 external circuitry for transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25 external circuitry for symmetrical receivers. . . . . . . . . . . . . . . . . . . . 51 figure 26 disabling of s/t transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27 external loop at the s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 28 clock system of the sbcx-x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29 phase relationships of sbcx-x clock signals . . . . . . . . . . . . . . . . . . 58 figure 30 buffered oscillator clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 31 layer-1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 32 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 33 state transition diagram (te, lt-t) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 34 state transition diagram of unconditional transitions (te, lt-t) . . . 64 figure 35 state transition diagram (lt-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 36 state transition diagram (nt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 37 example of activation/deactivation initiated by the terminal . . . . . . . 79 figure 38 example of activation/deactivation initiated by the terminal (te). activation/deactivation completely under software control . . . . . . . . 80
peb 3081 pef 3081 list of figures page data sheet 10 2000-09-27 figure 39 example of activation/deactivation initiated by the network termination (nt). activation/deactivation completely under software control . . . . . . . . 81 figure 40 iom ? -2 frame structure in terminal mode . . . . . . . . . . . . . . . . . . . . 83 figure 41 multiplexed frame structure of the iom-2 interface in non-te timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42 architecture of the iom handler (example configuration). . . . . . . . . . 86 figure 43 data access via cdax1 and cdax2 register pairs . . . . . . . . . . . . . . . 88 figure 44 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) shifting and looping data 89 figure 45 data access when looping tsa from du to dd . . . . . . . . . . . . . . . . . 90 figure 46 data access when shifting tsa to tsb on du (dd) . . . . . . . . . . . . . . 91 figure 47 example for monitoring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 48 interrupt structure of the synchronous data transfer . . . . . . . . . . . . . 94 figure 49 examples for the synchronous transfer interrupt control with one en- abled stixy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50 data strobe signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 51 strobed iom-2 bit clock. register sds_conf programmed to 01h . 98 figure 52 examples of monitor channel applications in iom-2 te mode . . . 99 figure 53 monitor channel protocol (iom-2) . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 54 monitor channel, transmission abort requested by the receiver. . . 104 figure 55 monitor channel, transmission abort requested by the transmitter. 104 figure 56 monitor channel, normal end of transmission . . . . . . . . . . . . . . . . . 105 figure 57 monitor interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 58 cic interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 59 applications of tic bus in iom-2 bus configuration . . . . . . . . . . . . . 111 figure 60 structure of last octet of ch2 on du . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 61 structure of last octet of ch2 on dd . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 62 d-channel access control on the s-interface . . . . . . . . . . . . . . . . . . 114 figure 63 data flow for collision resolution procedure in intelligent nt . . . . . 118 figure 64 deactivation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 65 activation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 66 register mapping of the sbcx-x . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 67 oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 68 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 69 iom-2 timing (te mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 70 iom-2 timing (lt-s, lt-t, nt mode) . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 71 definition of clock period and width . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 72 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 73 reset signal res . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
peb 3081 pef 3081 list of tables page data sheet 11 2000-09-27 table 1 comparison of the sbcx-x with the previous version sbcx: . . . . . . . 12 table 2 sbcx-x pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3 host interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4 header byte code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5 reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 6 sbcx-x timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7 s/q-bit position identification and multiframe structure . . . . . . . . . . . 42 table 8 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 9 examples for synchronous transfer interrupts . . . . . . . . . . . . . . . . . . 94 table 10 transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 11 receive direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 12 sbcx-x configuration settings in intelligent nt applications . . . . . . 116 table 13 aux pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 14 iom-2 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
peb 3081 pef 3081 overview data sheet 12 2000-09-27 preliminary 1 overview the s/t bus interface circuit extended (sbcx-x) implements the four-wire s/t interface used to link voice/data isdn terminals, network terminators and pbx trunk lines to a central office. it is the successor of the sbcx peb 2081 in 3.3 v technology. the sbcx-x provides the electrical and functional link between the analog s/t interface (compliant to the itu recommendation i.430) and the iom-2 interface. it provides an s/t interface operating in te, lt-t, lt-s, nt and intelligent nt modes, a serial control interface (sci) for host programming, three general purpose i/o pins and one led output which is capable to indicate the activation status of the s-interface automatically or can be programmed by the host. the sbcx-x is produced in advanced cmos technology. table 1 comparison of the sbcx-x with the previous version sbcx: sbcx-x peb 3081 sbcx peb 2081 operating modes te, lt-t, lt-s, nt, int. nt te, lt-t, lt-s, nt supply voltage 3.3v 5 % 5v 5 % technology cmos cmos package p-mqfp-44 / p-tqfp-48 p-lcc-28 / p-dip-28 transceiver transformer ratio for the transmitter receiver 1:1 1:1 2:1 2:1 test functions - analog loop (lp_a - bit exlp - bit, arl) - analog loop (arl) microcontroller interface serial interface (sci) not provided host programming sci or mon channel (monitor slave mode) mon channel (monitor slave mode) command structure of the register access header/address/data address/data crystal 7.68 mhz 7.68 mhz buffered 7.68 mhz output provided not provided
peb 3081 pef 3081 overview data sheet 13 2000-09-27 preliminary controller data access to iom-2 timeslots all timeslots; various possibilities of data access not provided data control and manipulation various possibilities of data control and data manipulation (enable/disable, shifting, looping, switching) shifting b-channel to channel 0 and direction control auxiliary interface aux0-2 (general purpose i/os) mai0-7 (general purpose i/os and several mode dependent functions) iom channel select (lt modes) channel select pins multiplexed on aux0-2 x0-2 led pin acl (host controlled or automatic indication of layer 1 activated state) not provided output pin for d-channel active indication provided not provided control input pin for d-channel inhibit provided not provided stop/go bit output pin provided provided iom-2 iom-2 interface double clock (dcl), bit clock (bcl), serial data strobe 1 (sds1) serial data strobe 2 (sds2) double clock (dcl), bit clock (bcl) monitor channel programming provided (mon0, 1, 2, ..., 7) provided (mon0 or 1) c/i channels ci0 (4bit), ci1 (4/6bit) ci0 (4bit), ci1 (6bit) table 1 comparison of the sbcx-x with the previous version sbcx: (cont?d) sbcx-x peb 3081 sbcx peb 2081
peb 3081 pef 3081 overview data sheet 14 2000-09-27 preliminary layer 1 state machine with changes for correspondence with the actual itu specification layer 1 state machine in software possible not possible reset signals res input signal rsto output signal rst input signal reset sources res input watchdog c/i code change eaw pin software reset rst input c/i code change interrupt output signals int low active (open drain) by default, reprogrammable to high active (push-pull) not provided table 1 comparison of the sbcx-x with the previous version sbcx: (cont?d) sbcx-x peb 3081 sbcx peb 2081
data sheet 15 2000-09-27 type package peb 3081 h p-mqfp-44 pef 3081 f p-tqfp-48 preliminary s/t bus interface circuit extended sbcx-x peb 3081 version 1.3 p-mqfp-44 p-tqfp-48 1.1 features full duplex 2b + d s/t interface transceiver according to itu-t i.430 successor of sbcx peb 2081 in 3.3v technology conversion of the frame structure between the s/t-interface and iom-2 iom-2 interface supporting te, lt-t, lt-s, nt and intelligent nt modes single and double clocks on iom-2 two serial data strobe signals serial control interface (sci) microcontroller access to all iom-2 timeslots monitor channel handler (master/slave) iom-2 monitor and c/i-channel protocol to control peripheral devices receive timing recovery d-channel access control activation and deactivation procedures with automatic activation from power down state access to s and q bits of s/t-interface adaptively switched receive thresholds 3 general purpose i/o pins multiplexed with channel select pins three pins for d-channel active indication, stop/go bit output and e-bit control on s one programmable timer watchdog timer software reset one led pin automatically indicating layer 1 activated state test loops sophisticated power management for restricted power mode
peb 3081 pef 3081 overview data sheet 16 2000-09-27 preliminary power supply 3.3 v 3.3 v output drivers, inputs are 5 v safe advanced cmos technology
peb 3081 pef 3081 overview data sheet 17 2000-09-27 preliminary 1.2 logic symbol the logic symbol gives an overview of the sbcx-x functions. it must be noted that not all functions are available simultaneously, but depend on the selected mode. pins which are marked with a ? * ? are multiplexed and not available in all modes. figure 1 logic symbol of the sbcx-x cs res int du scl sdr sdx rsto xtal2 xtal1 7.68 mhz output 7.68 mhz 100ppm sr1 sr2 sx1 sx2 s interface c768 dd fsc dcl bcl/ sclk vss vssa vdd vdda +3.3v 0v iom-2 interface host interface (sci) 3081_17 tp 0v sds1/2 aux0...2 * ch0...2 * acl led output iom channel select general purpose i/o auxiliary interface mode0 mode1 / eaw mode setting 2 dci dca sgo d-channel active indication d-channel inhibit s/g bit output
peb 3081 pef 3081 overview data sheet 18 2000-09-27 preliminary 1.3 typical applications the sbcx-x is designed for the user area of the isdn basic access. by programming the corresponding operating mode it may be used at both ends of these interfaces. figure 2 illustrates the general application fields of the sbcx-x: isdn terminals (te mode) isdn network termination (nt) for a link between the s/t interface and the u interface isdn subscriber line termination (lt-s) isdn trunk line termination (lt-t), i.e. pbx connection to central office figure 2 applications of the sbcx-x its04492 nt 2 1 nt nt 1 (1) te t su lt-s lt-t nt nt te (8) te (8) te (1) lt-s s network terminator (nt) = sbcx-x
peb 3081 pef 3081 pin configuration data sheet 19 2000-09-27 preliminary 2 pin configuration figure 3 pin configuration of the sbcx-x (p-mqfp-44) p-mqfp-44 sr2 sbcx-x peb 3081 12345 6 7891011 33 32 31 30 29 28 27 26 25 24 23 20 21 22 17 18 19 14 15 16 12 13 36 35 34 39 38 37 42 41 40 44 43 sr1 vdda vssa sx2 sx1 vss xtal2 xtal1 vss dca vdd int n.c. cs tp res rsto vss du dd fsc dcl vss vss vdd mode0 mode1 / eaw acl 3081_02.vsd vdd scl sdr vdd vss sds2 c768 sgo dci aux1 aux0 sds1 sdx aux2 bcl / sclk
peb 3081 pef 3081 pin configuration data sheet 20 2000-09-27 preliminary figure 4 pin configuration of the sbcx-x (p-tqfp-48) p-tqfp-48 sr2 sbcx-x peb 3081 12345 6 789101112 36 35 34 33 32 31 30 29 28 27 26 25 24 21 22 23 18 19 20 15 16 17 13 14 37 40 39 38 43 42 41 46 45 44 48 47 sr1 vdda vssa sx2 sx1 n.c. vss xtal2 xtal1 dca vss vdd int n.c. cs tp res rsto vss bcl / sclk du dd fsc dcl vss vss vdd mode0 mode1 / eaw acl n.c. 3081_01.vsd vdd n.c. scl sdr sdx n.c. vdd vss sds2 c768 sgo dci aux2 aux1 aux0 sds1
peb 3081 pef 3081 pin configuration data sheet 21 2000-09-27 preliminary table 2 sbcx-x pin definitions and functions pin no. symbol input (i) output (o) open drain (od) function mqfp- 44 tqfp- 48 host interface 910scli scl - serial clock clock signal of the sci interface if a serial interface is selected. 10 11 sdr i sdr - serial data receive receive data line of the sci interface if a serial interface is selected. 11 12 sdx od sdx - serial data transmit transmit data line of the sci interface if a serial interface is selected. 33cs i chip select a low level indicates a microcontroller access to the sbcx-x. 11int o (od) interrupt request int becomes active (low) if the sbcx-x requests an interrupt (open drain characteristic). the polarity can be reprogrammed to high active with push-pull characteristic. 55res i reset a low on this input forces the sbcx-x into a reset state. iom-2 interface 37 40 fsc i/o frame sync 8-khz frame synchronization signal. 38 41 dcl i/o data clock iom-2 interface clock signal (double clock, e.g. 1.536 mhz in te mode).
peb 3081 pef 3081 pin configuration data sheet 22 2000-09-27 preliminary 34 37 bcl/ sclk o bit clock/s-clock te-mode: bit clock output, identical to iom-2 data rate (dcl/2). lt-t mode: 1.536 mhz output synchronous to s- interface. nt / lt-s mode: bit clock output derived from the dcl input clock divided by 2. 36 39 dd i/o (od) data downstream iom-2 data signal in downstream direction. 35 38 du i/o (od) data upstream iom-2 data signal in upstream direction. 19 21 sds1 o serial data strobe 1 programmable strobe signal for time slot and/or d-channel indication on iom-2. 18 20 sds2 o serial data strobe 2 programmable strobe signal for time slot and/or d-channel indication on iom-2. miscellaneous 28 29 31 32 sx1 sx2 o o s-bus transmitter output (positive) s-bus transmitter output (negative) 32 33 35 36 sr1 sr2 i i s-bus receiver input s-bus receiver input 25 26 27 28 xtal1 xtal2 i o crystal 1 connection for a crystal or used as external clock input. 7.68 mhz clock or crystal required. crystal 2 connection for a crystal. not connected if an external clock is supplied to xtal1 table 2 sbcx-x pin definitions and functions (cont?d) pin no. symbol input (i) output (o) open drain (od) function mqfp- 44 tqfp- 48
peb 3081 pef 3081 pin configuration data sheet 23 2000-09-27 preliminary 20 21 22 22 23 24 aux0 aux1 aux2 i/o (od) i/o (od) i/o (od) te-mode: auxiliary port 0 - 2 (input/output) these pins are individually programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. lt-t/lt-s/nt mode: ch0-2 - iom-2 channel select (input) these pins select one of eight channels on the iom-2 interface. 42 45 mode0 i mode 0 select a low selects te-mode and a high selects lt-t / lt-s mode (see mode1/ eaw ). 43 46 mode1 eaw i i the pin function depends on the setting of mode0. if mode0=1: mode 1 select a low selects lt-t mode and a high selects lt-s mode. if mode0=0: external awake if a falling edge on this input is detected, the sbcx-x generates an interrupt and, if enabled, a reset pulse. 66rsto od reset output low active reset output, either from a watchdog timeout or programmed by the host. 17 19 c768 o clock output a 7.68 mhz clock is output to support other devices. this clock is not synchronous to the s interface. 14 16 dca o dca - d-channel active indication this pin provides an output of the d- channel bits on the s-bus receive line. table 2 sbcx-x pin definitions and functions (cont?d) pin no. symbol input (i) output (o) open drain (od) function mqfp- 44 tqfp- 48
peb 3081 pef 3081 pin configuration data sheet 24 2000-09-27 preliminary 15 17 dci i dci - d-channel inhibit if this bit is set to ? 1 ? the e-bits are inverted, i.e. the d-channel is blocked (only in nt/lt-s mode). this pin has the same function as the d-channel inhibit bit (see tr_mode.dch_inh). 16 18 sgo o sgo - stop/go bit output a s/g bit output with programmable polarity and length (tr_conf2 register) is provided. 44 47 acl o activation led this pin can either function as a programmable output or it can automatically indicate the activated state of the s interface by a logic ? 0 ? . an led with pre-resistance may directly be connected to acl . 44tp i test pin must be connected to v ss . 2 2, 9, 15, 30, 48 n.c. not connected power supply 8, 13, 23, 41 8, 14, 25, 44 v dd ? digital power supply voltage (3.3 v 5%) 31 34 v dda ? analog power supply voltage (3.3 v 5%) 7, 12, 24, 27, 39, 40 7, 13, 26, 29, 42, 43 v ss ? digital ground (0 v) 30 33 v ssa ? analog ground (0 v) table 2 sbcx-x pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) open drain (od) function mqfp- 44 tqfp- 48
peb 3081 pef 3081 description of functional blocks data sheet 25 2000-09-27 preliminary 3 description of functional blocks 3.1 general functions and device architecture figure 5 shows the architecture of the sbcx-x containing the following functions: s/t-interface transceiver supporting te, lt-t, lt-s, nt and intelligent nt modes serial control interface (sci) iom-2 interface for terminal, linecard and nt applications, with single/double clock two serial data strobe signals iom handler with controller data access registers (cda) allows flexible access to iom timeslots for reading/writing, looping and shifting data synchronous transfer interrupts (sti) allow controlled access to iom timeslots monitor channel handler on iom-2 for master mode, slave mode or data exchange c/i-channel handler d-channel access mechanism 3-pin auxiliary port for general purpose i/o pins or channel select pins led connected to pin acl indicates s-interface activation status automatically or can be controlled by the host output for d-channel active indication (output of received d-bits on s) stop/go bit output with programmable polarity and length d-channel inhibit input pin to control inversion of e-bits on s to block other terminals level detect circuit on the s interface reduces power consumption in power down mode timer for periodic or single interrupts clock and timing generation digital pll to synchronize the transceiver to the s/t interface buffered 7.68 mhz oscillator clock output allows connection of further devices and saves another crystal on the system board reset generation (watchdog timer)
peb 3081 pef 3081 description of functional blocks data sheet 26 2000-09-27 preliminary figure 5 functional block diagram of the sbcx-x reset interrupt generation iom-2 interface iom-2 handler s transceiver serial host interface (sci) osc dpll host peripheral devices 3081_18 auxiliary interface general purpose i/os c/i tic monitor handler
peb 3081 pef 3081 description of functional blocks data sheet 27 2000-09-27 preliminary 3.2 microcontroller interface the sbcx-x supports a serial micrcontroller interface. for applications where no controller is connected to the sbcx-x programming is done via the iom-2 monitor channel from a master device. in such applications the sbcx-x operates in the iom-2 slave mode (refer to the corresponding chapter of the iom-2 monitor handler). this mode is suitable for control functions (e.g. programming registers of the s/t transceiver), but the bandwidth is not sufficient to transfer b- and d-channel data. the interface selection is done by pinstrapping of the chip select signal cs (see table 3 ). the selection pins are evaluated when the reset input res is active. for the pin levels stated in the table the following is defined: ? high ? : dynamic pin; value must be ? high ? only during reset v ss : static pin; pin must statically be strapped to ? low ? level the interfaces contain all circuitry necessary for the access to programmable registers. the mapping of all these registers can be found in chapter 4 . the microcontroller interface also provides an interrupt request at pin int which is low active by default but can be reprogrammed to high active, a reset input pin res and a reset output pin rsto . the interrupt request pin int becomes active if the sbcx-x requests an interrupt and this can occur at any time. table 3 host interface selection cs interface mode ? high ? serial control interface (sci) v ss iom-2 monitor channel (slave mode)
peb 3081 pef 3081 description of functional blocks data sheet 28 2000-09-27 preliminary 3.2.1 serial control interface (sci) the serial control interface (sci) is compatible to the spi interface of motorola or siemens c510 family of microcontrollers. the sci consists of 4 lines: scl, sdx, sdr and cs . data is transferred via the lines sdr and sdx at the rate given by scl. the falling edge of cs indicates the beginning of a serial access to the registers. the sbcx-x latches incoming data at the rising edge of scl and shifts out at the falling edge of scl. each access must be terminated by a rising edge of cs . data is transferred in groups of 8 bits with the msb first. figure 6 shows the timing of a one byte read/write access via the serial control interface. figure 6 serial control interface timing 7 654321076543210 header address cs scl sdr sdx 7 654321 cs scl sdr sdx 76543210 data 0 data '0' write header address 7 654321 0 7 654321 0 '1' read 21150_19 write access read access
peb 3081 pef 3081 description of functional blocks data sheet 29 2000-09-27 preliminary 3.2.2 programming sequences the basic structure of a read/write access to the sbcx-x registers via the serial control interface is shown in figure 7 . figure 7 serial control interface timing a new programming sequence starts with the transfer of a header byte. the header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the sbcx-x. the possible sequences for access to the complete address range 00 h -7f h are listed in table 4 and described after that. note: in order to access the address range 00 h -7f h bit 2 of the header byte must be set to ?0? (header bytes 40 h , 48 h , 43 h , 41 h , 49 h ), and for the addresses 80 h -ff h bit 2 must be set to ?1? (header bytes 44 h , 4c h , 47 h , 45 h , 4d h ). table 4 header byte code header byte sequence sequence type 40 h /44 h adr-data-adr-data alternating read/write (non-interleaved) 48 h /4c h alternating read/write (interleaved) 43 h /47 h adr-data-data-data read-only/write-only (constant address) 41 h /45 h read and following write-only (non-interleaved) 49 h /4d h read and following write-only (interleaved) sdr write sequence: read sequence: sdr 7 076 07 0 write data address read data 0 1 write read 7 076 07 0 header byte 2 byte 3 header byte 2 byte 3 sdx address
peb 3081 pef 3081 description of functional blocks data sheet 30 2000-09-27 preliminary header 40 h : non-interleaved a-d-a-d sequences the non-interleaved a-d-a-d sequence gives direct read/write access to the complete address range and can have any length. in this mode sdx and sdr can be connected together allowing data transmission on one line. example for a read/write access with header 40 h : header 48 h : interleaved a-d-a-d sequences the interleaved a-d-a-d sequence gives direct read/write access to the complete address range and can have any length. this mode allows a time optimized access to the registers by interleaving the data on sdx and sdr (sdr and sdx must not be connected together). example for a read/write access with header 48 h : header 43 h : read-/write- only a-d-d-d sequence (constant address) this mode can be used for a fast access to the hdlc fifo data. any address (rdadr, wradr) in the range 00 h -1f h and 6a h /7a h gives access to the current fifo location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. the sequence can have any length and is terminated by the rising edge of cs . example for a write access with header 43 h : example for a read access with header 43 h : sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rdata sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx sdr header rdadr sdx rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr)
peb 3081 pef 3081 description of functional blocks data sheet 31 2000-09-27 preliminary header 41 h : non-interleaved a-d-d-d sequence this sequence allows in front of the a-d-d-d write access a non-interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . example for a read/write access with header 41 h : header 49 h : interleaved a-d-d-d sequence this sequence allows in front of the a-d-d-d write access an interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of the cs line. example for a read/write access with header 49 h : sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata
peb 3081 pef 3081 description of functional blocks data sheet 32 2000-09-27 preliminary 3.2.3 interrupt structure special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. since only one interrupt request pin (int ) is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the device. the structure of the interrupt status registers is shown in figure 8 . figure 8 interrupt status and mask registers all five interrupt bits in the ista register point at interrupt sources in the monitor handler (mos), c/i handler (cic), the transceiver (tran), the synchronous transfer (st) and the auxiliary interrupts (auxi). all these interrupt sources are described in the corresponding chapters. after the device has requested an interrupt activating the interrupt pin (int ), the host must read first the device interrupt status register (ista) in the associated interrupt service routine. the interrupt pin of the device remains active until all interrupt sources are cleared by reading the corresponding interrupt register. therefore it is possible that the interrupt pin is still active when the interrupt service routine is finished. each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the mask register. for some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. this can be done by masking all interrupts at the end of the interrupt service routine (writing ff h into the mask register) and write back the old mask to the mask register. mos tran aux cic st mos tran aux cic st sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti ack10 ack11 ack20 ack21 asti msti mie mre mab mda mer mdr sqw sqc ric ld masktr istatr sqw sqc ric ld mask ista 3081_16.vsd interrupt mocr mosr tin wov auxm auxi tin wov eaw eaw ci1e cic1 cic0 cix1 cir0
peb 3081 pef 3081 description of functional blocks data sheet 33 2000-09-27 preliminary 3.2.4 reset generation figure 9 shows the organization of the reset generation of the device. . figure 9 reset generation reset source selection the internal reset sources c/i code change, eaw and watchdog can be output at the low active reset pin rsto . the selection of these reset sources can be done with the rss2,1 bits in the mode1 register according table 5 . the setting rss2,1 = ? 01 ? is reserved for further use. in this case no reset except software reset (sres.rsto) is output on rsto . the internal reset sources set the mode1 register to its reset value. c/i code change (exchange awake) eaw (subscriber awake) watchdog 1 125s t 250s 125s t 250s software reset register (sres) reset functional block transceiver, c/i (22 h -3f h ) iom-2 (40 h -5b h ) mon-channel (5c h -5f h ) reset mode1 register internal reset of all registers 1 rss1 rss2,1 '0' '1' '1x' '00' rss2,1 '01' ' 01 ' pin rsto pin res 3081_21 (reserved) 1 125s t 250s 125s t 250s general config (60 h -6f h )
peb 3081 pef 3081 description of functional blocks data sheet 34 2000-09-27 preliminary c/i code change (exchange awake) a change in the downstream c/i channel (c/i0) generates an external reset pulse of 125s t 250s. eaw (subscriber awake) a low level on the eaw input starts the oscillator from the power down state and generates a reset pulse of 125s t 250s. watchdog timer after the selection of the watchdog timer (rss = ? 11 ? ) an internal timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1- and wtc2 bits in the following sequence to reset and restart the watchdog timer: if not, the timer expires and a wov-interrupt (ista register) together with a reset pulse of 125 s is generated. deactivation of the watchdog timer is only possible with a hardware reset. external reset input at the res input an external reset can be applied forcing the device in the reset state. this external reset signal is additionally fed to the rsto output. the length of the reset signal is specified in chapter 5.8 . after an external reset from the res pin all registers of the device are set to its reset values (see register description in chapter 4 ). software reset register (sres) every main functional block of the device can be reset separately by software setting the corresponding bit in the sres register. a reset to external devices can also be controlled in this way. the reset state is activated by setting the corresponding bit to ? 1 ? and onchip table 5 reset source selection rss2 bit 1 rss1 bit 0 c/i code change eaw watchdog timer 0 0 -- -- -- 0 1 reserved 10 x x -- 11 -- -- x wtc1 wtc2 1. 2. 1 0 0 1
peb 3081 pef 3081 description of functional blocks data sheet 35 2000-09-27 preliminary logic resets this bit again automatically after 4 bcl clock cycles. the address range of the registers which will be reset at each sres bit is listed in figure 9 . 3.2.5 timer modes the sbcx-x provides one timer which can be used for various purposes. it provides two modes ( table 6 ), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. when the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ista.aux. the source of the interrupt can be read from auxi.tin and masked in auxm. figure 10 timer interrupt status registers table 6 sbcx-x timer address register modes period 65 h timr periodic 1 ... 63 ms count down 1 ... 63 ms st mos tran aux interrupt ista mask mos tran aux st wov tin wov tin auxm auxi eaw eaw cic cic
peb 3081 pef 3081 description of functional blocks data sheet 36 2000-09-27 preliminary the host starts and stops the timer in timr.cnt ( figure 11 ). if timr.tmd=0 the timer is operating in count down mode, for timr.tmd=1 a periodic interrupt auxi.tin is generated. the timer length (for count down timer) or the timer period (for periodic timer), respectively, can be configured to a value between 1 - 63 ms (timr.cnt). figure 11 timer register 3081_14 cnt 7 6 5 4 3 2 1 0 65 h timer count 0 : timer off 1 ... 63 : 1 ... 63 ms timer mode 0 : count down timer 1 : periodic timer timr tmd 0
peb 3081 pef 3081 description of functional blocks data sheet 37 2000-09-27 preliminary 3.2.6 activation indication via pin acl the activated state of the s-interface is directly indicated via pin acl (activation led). an led with pre-resistance may directly be connected to this pin and a low level is driven on acl as soon as the layer 1 state machine reaches the activated state (see figure 12 ). figure 12 acl indication of activated layer 1 on te side by default (acfg2.acl=0) the state of layer 1 is indicated at pin acl . if the automatic indication of the activated layer 1 is not required, the state on pin acl can also be controlled by the host (see figure 13 ). if acfg2.acl=1 the led on pin acl can be switched on (acfg2.led=1) and off (acfg2.led=0) by the host. figure 13 acl configuration 3086_15 layer 1 acfg2:led 0 : off 1 : on acfg2:acl '1' '0' acl +3.3v s interface
peb 3081 pef 3081 description of functional blocks data sheet 38 2000-09-27 preliminary 3.3 s/t-interface the layer-1 functions for the s/t interface of the sbcx-x are: ? line transceiver functions for the s/t interface according to the electrical specifications of itu-t i.430; ? conversion of the frame structure between iom-2 and s/t interface; ? conversion from/to binary to/from pseudo-ternary code; ? level detection; ? receive timing recovery for point-to-point, passive bus and extended passive bus configuration; ? s/t timing generation using iom-2 timing synchronous to system, or vice versa; ? d-channel access control and priority handling; ? d-channel echo bit generation by handling of the global echo bit; ? activation/deactivation procedures, triggered by primitives received over the iom-2 interface or by infos received from the line; ? execution of test loops. the wiring configurations in user premises, in which the sbcx-x can be used, are illustrated in figure 14 .
peb 3081 pef 3081 description of functional blocks data sheet 39 2000-09-27 preliminary figure 14 wiring configurations in user premises 3081_20 sbcx-x tr te tr lt-s 1000 m 1) tr lt-t tr nt 1000 m 1) point-to-point configurations tr tr nt / lt-s 100 m tr te1 tr nt / lt-s 10 m extended passive bus te8 25 m 500 m .... te1 10 m te8 .... short passive bus tr: terminating resistor 1) the maximum line attenuation tolerated by the sbcx-x is 7 db at 96 khz. sbcx-x sbcx-x sbcx-x sbcx-x sbcx-x sbcx-x sbcx-x sbcx-x sbcx-x
peb 3081 pef 3081 description of functional blocks data sheet 40 2000-09-27 preliminary 3.3.1 s/t-interface coding transmission over the s/t-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (b1+b2+d), 48 kbit/s are used for framing and maintenance information. line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. figure 15 s/t-interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 16 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. 011 code violation
peb 3081 pef 3081 description of functional blocks data sheet 41 2000-09-27 preliminary figure 16 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multiframe f a
peb 3081 pef 3081 description of functional blocks data sheet 42 2000-09-27 preliminary 3.3.2 s/t-interface multiframing according to itu recommendation i.430 a multiframe provides extra layer 1 capacity in the te-to-nt direction by using an extra channel between the te and nt (q-channel). the q bits are defined to be the bits in the f a bit position. in the nt-to-te direction the s-channel bits are used for information transmission. one s channel (s1) out of five possible s-channels can be accessed by the sbcx-x. in the nt-to-te direction the s-channel bits are used for information transmission. the s and q channels are accessed via the c interface or the iom-2 monitor channel, respectively, by reading/writing the sqr or sqx bits in the s/q channel registers (sqrrx, sqxrx). table 7 shows the s and q bit positions within the multiframe. table 7 s/q-bit position identification and multiframe structure frame number nt-to-te f a bit position nt-to-te m bit nt-to-te s bit te-to-nt f a bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s11 s21 s31 s41 s51 q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s12 s22 s32 s42 s52 q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s13 s23 s33 s43 s53 q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s14 s24 s34 s44 s54 q4 zero zero zero zero 1 2 one zero one zero s11 s21 q1 zero
peb 3081 pef 3081 description of functional blocks data sheet 43 2000-09-27 preliminary te mode after multiframe synchronization has been established, the q data will be inserted at the upstream (te nt) f a bit position in each 5th s/t frame (see table 7 ). when synchronization is not achieved or lost, each received f a bit is mirrored to the next transmitted f a bit. multiframe synchronization is achieved after two complete multiframes have been detected with reference to f a /n bit and m bit positions. multiframe synchronization is lost if bit errors in f a /n bit or m bit positions have been detected in two consecutive multiframes. the synchronization state is indicated by the msyn bit in the s/q-channel receive register (sqrr1). the multiframe synchronization can be enabled or disabled by programming the mfen bit in the s/q-channel transmit register (sqxr1). nt mode the transceiver in nt mode starts multiframing if sqxr1.mfen is set. after multiframe synchronization has been established in the te, the q data will be inserted at the upstream (te nt) f a bit position by the te in each 5th s/t frame, the s data will be inserted at the downstream (nt te) s bit position in each s/t frame (see table 7 ). interrupt handling for multiframing to trigger the microcontroller for a multiframe access an interrupt can be generated once per multiframe (sqw) or if the received s-channels (te) or q-channel (nt) have changed (sqc). in both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms).
peb 3081 pef 3081 description of functional blocks data sheet 44 2000-09-27 preliminary 3.3.3 data transfer and delay between iom-2 and s/t te mode in the state f7 (activated) or if the internal layer-1 statemachine is disabled and xinf of register tr_cmd is programmed to ? 011 ? the b1, b2, d and e bits are transferred transparently from the s/t to the iom-2 interface. in all other states ? 1 ? s are transmitted to the iom-2 interface. to transfer data transparently to the s/t interface any activation request c/i command (ar8, ar10 or arl) is additionally necessary or if the internal layer-1 statemachine is disabled, bit tddis of register tr_cmd has additionally to be programmed to ? 0 ? . figure 17 shows the data delay between the iom-2 and the s/t interface and vice versa. for the d channel the delay from the iom-2 to the s/t interface is only valid if s/g evaluation is disabled (tr_mode2.dim0=0). if s/g evaluation is enabled (tr_mode2.dim2-0=0x1) the delay depends on the selected priority and the relation between the echo bits on s and the d channel bits on the iom-2, e.g. for priority 8 the timing relation between the 8th d-bit on s bus and the d-channel on iom-2. figure 17 data delay between iom-2 and s/t interface (te mode only) line_iom_s.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1
peb 3081 pef 3081 description of functional blocks data sheet 45 2000-09-27 preliminary figure 18 data delay between iom-2 and s/t interface with s/g bit evaluation (te mode only) lt-t mode in this mode the frame relation between s/t interface and iom-2 is flexible. lt-s/nt mode in the state f7 (activated) or if the internal layer-1 statemachine is disabled and xinf of register tr_cmd is programmed to ? 011 ? the b1, b2 and d bits are transferred transparently from the s/t to the iom-2 interface. in all other states ? 1 ? s are transmitted to the iom-2 interface. note: in intelligent nt the d-channel access can be blocked by the iom-2 d-channel handler. line_iom_s_dch.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 mapping of b-channel timeslots 1. possibility 2. possibility mapping of a 4-bit group of d-bits on s and iom depends on prehistory (e.g. priority control):
peb 3081 pef 3081 description of functional blocks data sheet 46 2000-09-27 preliminary figure 19 data delay between iom-2 and s/t interface with 8 iom channels (lt-s/nt mode only) figure 20 data delay between iom-2 and s/t interface with 3 iom channels and maximum receive delay (lt-s/nt mode only) b1 b2 d b1 b2 d b1 b2 d b1 b2 d line_iom_s4nt.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b1 b2 b2 f d d d d e e e e d d d d e e e e line_iom_s4nt_dly.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f e e e e b1 b1 b2 b2 f b1 b1 b2 b2 f d d d d d d d d te -> nt (42s) b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1
peb 3081 pef 3081 description of functional blocks data sheet 47 2000-09-27 preliminary 3.3.4 transmitter characteristics the full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source (v sx1/sx2 = +/-1.05v; i max = 26 ma). the equivalent circuit of the transmitter is shown in figure 21 . the nominal pulse amplitude on the s-interface of 750 mv (zero-peak) is adjusted with external resistors (see chapter 3.3.6.1 ). figure 21 equivalent internal circuit of the transmitter stage 21150_28 level '+0' '-0' '1' '+0' '-0' '1' vcm+0.525v vcm-0.525v vcm vcm-0.525v vcm+0.525v vcm tr_conf2.dis_tx '+0' '1' '-0' + - v=1 vcm - + v=1 sx2 sx1
peb 3081 pef 3081 description of functional blocks data sheet 48 2000-09-27 preliminary 3.3.5 receiver characteristics the receiver consists of a differential input stage, a peak detector and a set of comparators. additional noise immunity is achieved by digital oversampling after the comparators. a simplified equivalent circuit of the receiver is shown in figure 22 . figure 22 equivalent internal circuit of the receiver stage the input stage works together with external 10 k ? resistors to match the input voltage to the internal thresholds. the data detection threshold vref is continuously adapted between a maximal (vrefmax) and a minimal (vrefmin) reference level related to the line level. the peak detector requires maximum 2 s to reach the peak value while storing the peak level for at least 250 s (rc > 1 ms). the additional level detector for power up/down control works with a fixed threshold vrefld. the level detector monitors the line input signals to detect whether an info is present. when closing an analog loop it is therefore possible to indicate an incoming signal during activated loop. 100 kohm
peb 3081 pef 3081 description of functional blocks data sheet 49 2000-09-27 preliminary 3.3.6 s/t interface circuitry for both, receive and transmit direction a 1:1 transformer is used to connect the sbcx- x transceiver to the 4 wire s/t interface. typical transformer characteristics can be found in the chapter on electrical characteristics. the connections of the line transformers is shown in figure 23 . figure 23 connection of line transformers and power supply to the sbcx-x for the transmit direction an external transformer is required to provide isolation and pulse shape according to the itu-t recommendations. 3.3.6.1 external protection circuitry the itu-t i.430 specification for both transmitter and receiver impedances in tes results in a conflict with respect to external s-protection circuitry requirements: ? to avoid destruction or malfunction of the s-device it is desirable to drain off even small overvoltages reliably. ? to meet the 96 khz impedance test specified for transmitters and receivers (for tes only, itu-t i.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be dimensioned such that voltages below 1.2 v (itu-t i.430 amplitude) x transformer ratio are not affected. this requirement results from the fact that this test is also to be performed with no supply voltage being connected to the te. therefore the second reference point for overvoltages v dd , is tied to gnd. then, if the amplitude of the 96 khz test signal is greater than the combined forward voltages of the diodes, a current exceeding the specified one may pass the protection circuit. the following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 khz impedance tests. 21150_05 protection circuit protection circuit 1:1 1:1 transmit pair receive pair sx1 sx2 sr1 sr2 gnd vdd vss 3.3 v 10 f
peb 3081 pef 3081 description of functional blocks data sheet 50 2000-09-27 preliminary protection circuit for transmitter figure 24 external circuitry for transmitter figure 24 illustrates the secondary protection circuit recommended for the transmitter. the external resistors (r = 5 .... 10 ? ) are required in order to adjust the output voltage to the pulse mask on the one hand and in order to meet the output impedance of minimum 20 ? (transmission of a binary zero according to itu-t i.430) on the other hand. two mutually reversed diode paths protect the device against positive or negative overvoltages on both lines. an ideal protection circuit should limit the voltage at the sx pins from ? 0.4 v to v dd + 0.4 v. with the circuit in figure 24 the pin voltage range is increased from ? 1.4 v to v dd + 0.7 v. the resulting forward voltage of 1.4 v will prevent the protection circuit from becoming active if the 96 khz test signal is applied while no supply voltage is present. sx1 vdd s bus 1:1 3081_23 sx2 r r
peb 3081 pef 3081 description of functional blocks data sheet 51 2000-09-27 preliminary protection circuit for receiver figure 25 illustrates the external circuitry used in combination with a symmetrical receiver. protection of symmetrical receivers is rather simple. figure 25 external circuitry for symmetrical receivers between each receive line and the transformer a 10 k ? = resistor is used. this value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 khz test, and the second one between input pin and protection diodes to limit the maximum input current of the chip. with symmetrical receivers no difficulties regarding lcl measurements are observed; compensation networks thus are obsolete. in order to comply to the physical requirements of itu-t recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the sbcx-x may need additional circuitry. 3.3.7 s/t interface delay compensation (te/lt-t mode) the s/t transmitter is shifted by two s/t bits minus 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. to compensate additional delay introduced into the receive and transmit path by the external circuit the delay of the transmit data can be reduced by another two oscillator periods (2 x 130 ns). therefore pds of the tr_conf2 register must be programmed to ? 1 ? . this delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of itu-t recommendation i.430 which specifies a phase deviation in the range of ? 7% to + 15% of a bit period. note: up to 10 pf capacitors are optional for noise reduction 1:1
peb 3081 pef 3081 description of functional blocks data sheet 52 2000-09-27 preliminary 3.3.8 level detection power down if mode1.cfs is set to ? 0 ? , the clocks are also provided in power down state, whereas if cfs is set to ? 1 ? only the analog level detector is active in power down state. all clocks, including the iom-2 interface, are stopped (dd, du are ? high ? , dcl and bcl are ? low ? ). an activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if tr_conf0.ldd is set to ? 0 ? . if tr_conf0.ldd is set to ? 1 ? the microcontroller has to take care of an interrupt caused by the level detect circuit (istatr.ld) from the terminal side an activation must be started by setting and resetting the spu- bit in the iom_cr register and writing tim to the cix0 register or by resetting mode1.cfs=0. 3.3.9 transceiver enable/disable the layer-1 part of the sbcx-x can be enabled/disabled by configuration (see figure 26 ) with the two bits tr_conf0.dis_tr and tr_conf2.dis_tx . by default all layer-1 functions with the exception of the transmitter buffer is enabled (dis_tr = ? 0 ? , dis_tx = ? 1 ? ). with several terminals connected to the s/t interface, another terminal may keep the interface activated although the sbcx-x does not establish a connection. the receiver will monitor for incoming calls in this configuration. if the transceiver is disabled (dis_tr = ? 1 ? ) all layer-1 functions are disabled including the level detection circuit of the receiver. in this case the power consumption of the layer-1 is reduced to a minimum. the dcl and fsc pins become input. figure 26 disabling of s/t transmitter tr_conf2.dis_tx ? 1 ? ? 0 ? tr_conf0.dis_tr
peb 3081 pef 3081 description of functional blocks data sheet 53 2000-09-27 preliminary 3.3.10 test functions the sbcx-x provides test and diagnostic functions for the s/t interface: ? the internal local loop (internal loop a) is activated by a c/i command arl or by setting the bit lp_a (loop analog) in the tr_cmd register if the layer-1 statemachine is disabled. the transmit data of the transmitter is looped back internally to the receiver. the data of the iom-2 input b- and d-channels are looped back to the output b- and d- channels. the s/t interface level detector is enabled, i.e. if a level is detected this will be reported by the resynchronization indication (rsy) but the loop function is not affected. depending on the dis_tx bit in the tr_conf2 register the internal local loop can be transparent or non transparent to the s/t line. ? the external local loop (external loop a) is activated in the same way as the internal local loop described above. additionally the exlp bit in the tr_conf0 register has to be programmed and the loop has to be closed externally as described in figure 27 . the s/t interface level detector is disabled. this allows complete system diagnostics. ? in remote line loop (rlp) received data is looped back to the s/t interface. the d- channel information received from the line card is transparently forwarded to the output iom-2 d-channel. the output b-channel information on iom-2 is fixed to ? ff ? h while this test loop is active. the remote loop is programmable in tr_conf2.rlp. figure 27 external loop at the s/t-interface scout-s(x) sx1 sx2 sr1 sr2 100 ? 100 ?
peb 3081 pef 3081 description of functional blocks data sheet 54 2000-09-27 preliminary ? transmission of special test signals on the s/t interface according to the modified ami code are initiated via a c/i command written in cix0 register (see chapter 3.5.4 ) two kinds of test signals may be transmitted by the sbcx-x: ? the single pulses are of alternating polarity. one pulse is transmitted in each frame resulting in a frequency of the fundamental mode of 2 khz. the corresponding c/i command is ssp (send single pulses). ? the continuous pulses are of alternating polarity. 48 pulses are transmitted in each frame resulting in a frequency of the fundamental mode of 96 khz. the corresponding c/i command is scp (send continuous pulses).
peb 3081 pef 3081 description of functional blocks data sheet 55 2000-09-27 preliminary 3.4 clock generation figure 28 shows the clock system of the sbcx-x. the oscillator is used to generate a 7.68 mhz clock signal (f xtal ). in te mode the dpll generates the iom-2 clocks fsc (8 khz), dcl (1536 khz) and bcl (768 khz) synchronous to the received s/t frames. in lt modes these pins are input and in lt-t mode an 1536 khz clock synchronous to s is output at sclk which can be used for dcl input. the fsc signal is used to generate the pulse lengths of the different reset sources c/i code, eaw pin and watchdog (see chapter 3.2.4 ). figure 28 clock system of the sbcx-x 3081_06 osc xtal 7.68 mhz dpll reset generation sw reset c/i eaw watchdog f xtal fsc (te mode) dcl (te mode) bcl (te mode) sclk (lt-t mode) 125 s t 250 s 125 s t 250 s 125 s t 250 s pin rsto 125 s t 250 s
peb 3081 pef 3081 description of functional blocks data sheet 56 2000-09-27 preliminary table 8 clock modes te lt-t lt-s nt int. nt selected via pin: mode0=0 pin:mode1=0 mode0=1 pin:mode1=1 mode0=1 bit:mode2=0 mode1=1 mode0=0 bit:mode2=1 mode1=1 mode0=1 or mode0=0 *1) fsc o:8 khz i:8 khz i:8 khz i:8 khz i:8 khz dcl o:1536 khz i:1536 khz (from sclk) or 4096 khz (from ext. pll) i:512 khz or 1536 khz or 4096 khz i:512 khz or 1536 khz or 4096 khz i:1536 khz bcl/sclk o:768 khz (bcl) o:1536 khz (sclk) *3) o:256 khz or 768 khz or 2048 khz (derived from dcl/2) o:256 khz or 768 khz or 2048 khz (derived from dcl/2) o:768 khz (derived from dcl/2) du *4) i i ooo ddooiii aux0-2 general purpose i/o pins ch0-2: strap pins for iom channel select *2) ch0-2: strap pins for iom channel select *2) ch0-2: strap pins for iom channel select *2) general purpose i/o pins
peb 3081 pef 3081 description of functional blocks data sheet 57 2000-09-27 preliminary note: i = input; o = output; for all input clocks typical values are given although other clock frequencies may be used, too. 1) the modes te, lt-t and lt-s can directly be selected by strapping the pins mode1 and mode0. the mode can be reprogrammed in tr_mode.mode2-0 where nt and intelligent nt can be selected additionally. in int. nt mode mode0 selects between nt state machine (0) and lt-s state machine (1). 2) the number of iom channels depends on the dcl clock, e.g. with dcl=1536 khz 3 iom channels and with dcl=4096 khz 8 channels are available. 3) in lt-t mode the 1536 khz output clock on sclk is synchronous to the s interface and can be used as input for the dcl clock. 4) the direction input/output refers to the direction of the b- and d-channel data stream across the s-transceiver. due to the capabilites of the iom-2 handler the direction of some other timeslots may be different if this is programmed by the host (e.g. for data exchange between different devices connected to iom-2).
peb 3081 pef 3081 description of functional blocks data sheet 58 2000-09-27 preliminary 3.4.1 description of the receive pll (dpll) the receive pll performs phase tracking between the f/l transition of the receive signal and the recovered clock. phase adjustment is done by adding or subtracting 0.5 or 1 xtal period to or from a 1.536-mhz clock cycle. the 1.536-mhz clock is than used to generate any other clock synchronized to the line. during (re)synchronization an internal reset condition may effect the 1.536-mhz clock to have high or low times as short as 130 ns. after the s/t interface frame has achieved the synchronized state (after three consecutive valid pairs of code violations) the fsc output in te mode is set to a specific phase relationship, thus causing once an irregular fsc timing. the phase relationships of the clocks are shown in figure 29 . figure 29 phase relationships of sbcx-x clock signals 3.4.2 jitter the timing extraction jitter of the sbcx-x conforms to itu-t recommendation i.430 ( ? 7% to + 7% of the s-interface bit period). itd09664 7.68 mhz 1536 khz * 768 khz * synchronous to receive s/t. duty ratio 1:1 normally f-bit fsc
peb 3081 pef 3081 description of functional blocks data sheet 59 2000-09-27 preliminary 3.4.3 oscillator clock output c768 the sbcx-x derives its system clocks from an external clock connected to xtal1 (while xtal2 is not connected) or from a 7.68 mhz crystal connected across xtal1 and xtal2. at pin c768 a buffered 7.68 mhz output clock is provided to drive further devices, which is suitable in multiline applications for example (see figure 30 ). this clock is not synchronized to the s-interface. in power down mode the c768 output is disabled (low signal). figure 30 buffered oscillator clock output 3086_12 xtal1 xtal2 c768 xtal1 xtal2 c768 xtal1 xtal2 c768 7.68 mhz n.c. n.c. n.c. n.c.
peb 3081 pef 3081 description of functional blocks data sheet 60 2000-09-27 preliminary 3.5 control of layer-1 the layer-1 activation / deactivation can be controlled by an internal state machine via the iom-2 c/i0 channel or by software via the microcontroller interface directly. in the default state the internal layer-1 state machine of the sbcx-x is used. by setting the l1sw bit in the tr_conf0 register the internal state machine can be disabled and the layer-1 commands, which are normally generated by the internal state machine are written directly in the tr_cmd register or indications read from the tr_sta register respectively.the sbcx-x layer-1 control flow is shown in figure 31 . figure 31 layer-1 control in the following sections the layer-1 control by the sbcx-x state machine will be described. for the description of the iom-2 c/i0 channel see also chapter 3.7.4 . the layer-1 functions are controlled by commands issued via the cix0 register. these commands, sent over the iom-2 c/i channel 0 to layer-1, trigger certain procedures, such as activation/deactivation, switching of test loops and transmission of special pulse patterns. these procedures are governed by layer-1 state diagrams. responses from layer 1 are obtained by reading the cir0 register after a cic interrupt (ista). the state diagrams of the sbcx-x are shown in figure 33 and figure 34 . the activation/deactivation implemented by the sbcx-x agrees with the requirements set forth in itu recommendations. state identifiers f1-f8 are in accordance with itu i.430.
peb 3081 pef 3081 description of functional blocks data sheet 61 2000-09-27 preliminary state machines are the key to understanding the transceiver part of the sbcx-x. they include all information relevant to the user and enable him to understand and predict the behaviour of the sbcx-x. the state diagram notation is given in figure 32 . the informations contained in the state diagrams are: ? state name (based on itu i.430) ? s/t signal received (info) ? s/t signal transmitted (info) ? c/i code received ? c/i code transmitted ? transition criteria the coding of the c/i commands and indications are described in detail in chapter 3.5.4 . figure 32 state diagram notation the following example illustrates the use of a state diagram with an extract of the te state diagram. the state explained is ? f3 deactivated ? . the state may be entered: ? from the unconditional states (arl, res, tm) ? from state ? f3 pending deactivation ? , ? f3 power up ? , ? f4 pending activation ? or ? f5 unsynchronized ? after the c/i command ? di ? has been received. the following informations are transmitted: ? info 0 (no signal) is sent on the s/t-interface. ? c/i message ? dc ? is issued on the iom-2 interface. itd09657 cmd. ind. state c / unconditional transition s / t interface info out ipac in i x i r ipac iom-2 interface sbcx-x
peb 3081 pef 3081 description of functional blocks data sheet 62 2000-09-27 preliminary the state may be left by either of the following methods: ? leave for the state ? f3 power up ? in case c/i = ? tim ? code is received. ? leave for state ? f4 pending activation ? in case c/i = ar8 or ar10 is received. ? leave for the state ? f6 synchronized ? after info 2 has been recognized on the s/t- interface. ? leave for the state ? f7 activated ? after info 4 has been recognized on the s/t- interface. ? leave for any unconditional state if any unconditional c/i command is received. as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? ? stands for a logical and combination. and a ? + ? indicates a logical or combination. the sections following the state diagram contain detailed information on all states and signals used. 3.5.1 state machine te and lt-t mode 3.5.1.1 state transition diagram (te, lt-t) figure 33 shows the state transition diagram of the sbcx-x state machine. figure 34 shows this for the unconditional transitions (reset, loop, test mode i).
peb 3081 pef 3081 description of functional blocks data sheet 63 2000-09-27 preliminary figure 33 state transition diagram (te, lt-t) x 1) dr for transition from f7 or f8 dr6 for transition from f6 2) ar stands for ar8 or ar10 3) ai stands for ai8 or ai10 4) x stands for commands initiating unconditional transitions (res, arl, ssp or scp) to1: 16 ms to2: 0.5 ms statem_te_s.vsd f3 pending deact. dr 1) i0 i0 f3 deactivated dc di i0 i0 ar i2 tim i0*to1 f3 power up pu tim i0 i0 di tim di i2 di*to2 tim*to2 i0 f8 lost framing rsy i0 x i4 i0*to1 i0*to1 ar di i2 f7 activated ai 3) ar 2) i3 i4 f6 synchronized ar i3 i2 x f5 unsynchronized rsy i0 ix i2 i0 f4 pending act. pu ar 2) i1 i0 x i4 i2 i2 i4 ix ix tim i4 i4 i4 tim di tim x 4) uncond. state x di
peb 3081 pef 3081 description of functional blocks data sheet 64 2000-09-27 preliminary figure 34 state transition diagram of unconditional transitions (te, lt-t) 3.5.1.2 states (te, lt-t) f3 pending deactivation state after deactivation from the s/t interface by info 0. note that no activation from the terminal side is possible starting from this state. a ? di ? command has to be issued to enter the state ? deactivated state ? . f3 deactivated state the s/t interface is deactivated and the clocks are deactivated 500 s after entering this state and receiving info 0 if the cfs bit of the sbcx-x configuration register is set to ? 0 ? . activation is possible from the s/t interface and from the iom-2 interface. the bit tr_cmd.pd is set and the analog part is powered down. f3 power up the s/t interface is deactivated (info 0 on the line) and the clocks are running. f4 pending activation the sbcx-x transmits info 1 towards the network, waiting for info 2. statem_te_aloop_s.vsd loop a activated ail rsy arl i3 * loop a closed arl arl i3 * di tim di tim arl reset res res i0 * di tim ssp scp test mode i tma ssp scp it i * di tim i3 i3 res any state rst
peb 3081 pef 3081 description of functional blocks data sheet 65 2000-09-27 preliminary f5 unsynchronized any signal except info 2 or 4 detected on the s/t interface. f6 synchronized the receiver has synchronized and detects info 2. info 3 is transmitted to synchronize the nt. f7 activated the receiver has synchronized and detects info 4. all user channels are now conveyed transparently to the iom-2 interface. to transfer user channels transparently to the s/t interface either the command ar8 or ar10 has to be issued and tr_sta.fsyn must be ? 1 ? (signal from remote side must be synchronous). f8 lost framing the receiver has lost synchronization in the states f6 or f7 respectively. unconditional states loop a closed (internal or external) the sbcx-x loops back the transmitter to the receiver and activates by transmission of info 3. the receiver has not yet synchronized. for a non transparent internal loop the dis_tx bit of register tr_conf2 has to be set to ? 1 ? . loop a activated (internal or external) the receiver has synchronized to info 3. data may be sent. the indication ? ail ? is output to indicate the activated state. if the loop is closed internally and the s/t line awake detector detects any signal on the s/t interface, this is indicated by ? rsy ? . test mode - ssp single alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 2 khz. test mode - scp continuous alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 96 khz.
peb 3081 pef 3081 description of functional blocks data sheet 66 2000-09-27 preliminary 3.5.1.3 c/i codes (te, lt-t) note: in the activated states (ai8, ai10 or ail indication) the 2b+d channels are only transferred transparently to the s/t interface if one of the three ? activation request ? commands is permanently issued. command abbr. code remark activation request with priority class 8 ar8 1000 activation requested by the sbcx-x, d-channel priority set to 8 ( see note ) activation request with priority class 10 ar10 1001 activation requested by the sbcx-x, d-channel priority set to 10 ( see note ) activation request loop arl 1010 activation requested for the internal or external loop a ( see note ). for a non transparent internal loop bit dis_tx of register tr_conf2 has to be set to ? 1 ? additionally. deactivation indication di 1111 deactivation indication reset res 0001 reset of the layer-1 statemachine timing tim 0000 layer-2 device requires clocks to be activated test mode ssp ssp 0010 one ami-coded pulse transmitted in each frame, resulting in a frequency of the fundamental mode of 2 khz test mode scp scp 0011 ami-coded pulses transmitted continuously, resulting in a frequency of the fundamental mode of 96 khz indication abbr. code remark deactivation request dr 0000 deactivation request via s/t-interface if left from f7/f8 reset res 0001 reset acknowledge test mode acknowledge tma 0010 acknowledge for both ssp and scp slip detected sld 0011 resynchronization during level detect rsy 0100 signal received, receiver not synchronous
peb 3081 pef 3081 description of functional blocks data sheet 67 2000-09-27 preliminary deactivation request from f6 dr6 0101 deactivation request from state f6 power up pu 0111 iom-2 interface clocking is provided activation request ar 1000 info 2 received activation request loop arl 1010 internal or external loop a closed illegal code violation cvr 1011 illegal code violation received. this function has to be enabled by setting the en_icv bit of register tr_conf0. activation indication loop ail 1110 internal or external loop a activated activation indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9. activation indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11. deactivation confirmation dc 1111 clocks are disabled if cfs bit of register mode1 is set to ? 1 ? , quiescent state indication abbr. code remark
peb 3081 pef 3081 description of functional blocks data sheet 68 2000-09-27 preliminary 3.5.1.4 infos on s/t (te, lt-t) receive infos on s/t (downstream) transmit infos on s/t (upstream) name abbr. description info 0 i0 no signal on s/t info 2 i2 4 khz frame a= ? 0 ? info 4 i4 4 khz frame a= ? 1 ? info x ix any signal except info 2 or info 4 name abbr. description info 0 i0 no signal on s/t info 1 i1 continuous bit sequence of the form ? 00111111 ? info 3 i3 4 khz frame test info 1 it 1 ssp - send single pulses test info 2 it 2 scp - send continuous pulses
peb 3081 pef 3081 description of functional blocks data sheet 69 2000-09-27 preliminary 3.5.2 state machine lt-s mode 3.5.2.1 state transition diagram (lt-s) figure 35 state transition diagram (lt-s) g3 activated ai dc ard i4 i3 reset tim res i0 * g2 pend. act. ar dc ard i2 i3 g2 lost framing s/t rsy dc ard i2 i3 g1 deactivated di tim 2) dc i0 i0 1) ard = ar or arl statem_lts_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim ssp scp it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc ssp scp any state dr dc any state res ard 1) ard 1) dr i3 dr dr i3 i3 rst (i0*8ms)+ard 1) 2) di if i0 tim if i0
peb 3081 pef 3081 description of functional blocks data sheet 70 2000-09-27 preliminary 3.5.2.2 states (lt-s) g1 deactivated the transceiver is not transmitting. there is no signal detected on the s/t interface, and no activation command is received in the c/i channel. the clocks are deactivated if mode1.cfs is set to 1. activation is possible from the s/t interface and from the iom- 2 interface. g2 pending activation as a result of an info 0 detected on the s/t line or an ard command, the transceiver begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. g3 activated normal state where info 4 is transmitted to the s/t-interface. the transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter keeps on sending info 4. g2 lost framing this state is reached when the transceiver has lost synchronism in the state g3 activated. g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: indication di (state ? g4 wait for dr. ? ) is issued by the transceiver when: either info 0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the transceiver remains in this state until dc is issued.
peb 3081 pef 3081 description of functional blocks data sheet 71 2000-09-27 preliminary unconditional states test mode - ssp single alternating pulses are sent on the s/t-interface. test mode - scp continuous alternating pulses are sent on the s/t-interface. 3.5.2.3 c/i codes (lt-s) command abbr. code remark deactivation request dr 0000 dr - deactivation request. initiates a complete deactivation from the exchange side by transmitting info 0. reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos. res is an unconditional command. send single pulses ssp 0010 send single pulses. send continuous pulses scp 0011 send continuous pulses. activation request ar 1000 activation request. this command is used to start an exchange initiated activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled).
peb 3081 pef 3081 description of functional blocks data sheet 72 2000-09-27 preliminary indication abbr. code remark timing tim 0000 interim indication during activation procedure in g1. reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos. res is an unconditional command. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code violation cvr 1011 illegal code violation received. this function has to be enabled in tr_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request
peb 3081 pef 3081 description of functional blocks data sheet 73 2000-09-27 preliminary 3.5.2.4 infos on s/t (lt-s) receive infos on s/t (downstream) i0 info 0 detected i0 level detected (signal different to i0) i3 info 3 detected i3 any info other than info 3 transmit infos on s/t (upstream) i0 info 0 i2 info 2 i4 info 4 it send single pulses (ssp). send continuous pulses (scp).
peb 3081 pef 3081 description of functional blocks data sheet 74 2000-09-27 preliminary 3.5.3 state machine nt mode 3.5.3.1 state transition diagram (nt) figure 36 state transition diagram (nt) g2 pend. act ar ard i2 i3 reset tim res i0 * g1 i0 detected ar dc i0 * g2 lost framing s/t rsy aid ard i2 i3 g1 deactivated di tim 3) dc i0 i0 statem_nt_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim ssp scp it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc ssp scp any state dr dc any state res ard 1) ard 1) dr i3 i3*aid 2) rst ard 1) g2 wait for aid ai ard i2 i3 g3 lost framing u rsy rsy i2 * g3 activated ai aid i4 i3 ard 1) aid 2) i3*ard 1) i3*ard dr dr dr rsy rsy dr rsy ard 1) aid 2) 1) ard = ar or arl 2) aid =ai or ail 3) di if i0 tim if i0 ard 1) i3*aid 2) (i0*8ms)
peb 3081 pef 3081 description of functional blocks data sheet 75 2000-09-27 preliminary 3.5.3.2 states (nt) g1 deactivated the transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. the clocks are deactivated if the bit mode1.cfs is set to 1. activation is possible from the s/t interface and from the iom-2 interface. g1 i0 detected an info 0 is detected on the s/t-interface, translated to an ? activation request ? indication in the c/i channel. the transceiver is waiting for an ar command, which normally indicates that the transmission line upstream (usually a two-wire u interface) is synchronized. g2 pending activation as a result of the ard command, an info 2 is sent on the s/t-interface. info 3 is not yet received. in case of arl command, loop 2 is closed. g2 wait for aid info 3 was received, info 2 continues to be transmitted while the transceiver waits for a ? switch-through ? command aid from the device upstream. g3 activated info 4 is sent on the s/t-interface as a result of the ? switch through ? command aid: the b and d-channels are transparent. on the command ail, loop 2 is closed. g2 lost framing s/t this state is reached when the transceiver has lost synchronism in the state g3 activated. g3 lost framing u on receiving an rsy command which usually indicates that synchronization has been lost on the two-wire u interface, the transceiver transmits info 2.
peb 3081 pef 3081 description of functional blocks data sheet 76 2000-09-27 preliminary g4 pending deactivation this state is triggered by a deactivation request dr, and is an unstable state. indication di (state ? g4 wait for dr ? ) is issued by the transceiver when: either info 0 is received for a duration of 16 ms or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the transceiver remains in this state until dc is issued. unconditional states test mode ssp send single pulses test mode scp send continuous pulses 3.5.3.3 c/i codes (nt) command abbr. code remark deactivation request dr 0000 dr - deactivation request. initiates a complete deactivation from the exchange side by transmitting info 0. unconditional command. reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos. res is an unconditional command. send single pulses ssp 0010 send single pulses. send continuous pulses scp 0011 send continuous pulses. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 activation request. this command is used to start an exchange initiated activation.
peb 3081 pef 3081 description of functional blocks data sheet 77 2000-09-27 preliminary activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. activation indication ai 1100 synchronous receiver, i.e. activation completed. activation indication loop ail 1110 activation indication loop deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during deactivation procedure reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos. res is an unconditional command. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code violation cvr 1011 illegal code violation received. this function has to be enabled in tr_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request command abbr. code remark
peb 3081 pef 3081 description of functional blocks data sheet 78 2000-09-27 preliminary 3.5.4 command / indicate channel codes (c/i0) - overview the table below presents all defined c/i0 codes. a command needs to be applied continuously until the desired action has been initiated. indications are strictly state orientated. refer to the state diagrams in the previous sections for commands and indications applicable in various states. code te/lt-t lt-s nt cmd ind cmd ind cmd ind 0000tim dr dr tim dr tim 0 0 0 1 res res res res res res 0010ssp tma ssp ? ssp ? 0011scp sld scp ? scp ? 0100 ? rsy ? rsy rsy rsy 0101 ? dr6 ???? 0110 ?????? 0111 ? pu ???? 1 0 0 0 ar8 ar ar ar ar ar 1001ar10 ????? 1010arl arl arl ? arl ? 1011 ? cvr ? cvr ? cvr 1100 ? ai8 ? ai ai ai 1101 ? ai10 ???? 1110 ? ail ?? ail ? 1111di dcdcdi dcdi
peb 3081 pef 3081 description of functional blocks data sheet 79 2000-09-27 preliminary 3.6 control procedures 3.6.1 example of activation/deactivation an example of an activation/deactivation of the s/t interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 37 . figure 37 example of activation/deactivation initiated by the terminal a_deact.dr w
peb 3081 pef 3081 description of functional blocks data sheet 80 2000-09-27 preliminary 3.6.2 activation initiated by the terminal info 1 has to be transmitted as long as info 0 is received. info 0 has to be transmitted thereafter as long as no valid info (info 2 or info 4) is received. after reception of info 2 or info 4 transmission of info 3 has to be started. data can be transmitted if info 4 has been received. figure 38 example of activation/deactivation initiated by the terminal (te). activation/deactivation completely under software control note: rinf and xinf are receive- and transmit-infos of the registers tr_sta tr_cmd. act_deac_te-ext_s.vsd xinf='000' rinf='01' rinf='10' xinf='011' info 1 info 0 info 2 info 0 info 3 info 4 xinf='010' t1 te info 0 info 0 info 0 xinf='000' te nt s/t interface c interface t1 te : 2 to 6 frames (0.5 ms to 1.5 ms) t3 te : 4 frames (1 ms) t2 te : 2 frames (0.5 ms) t3 te rinf='00' t2 te rinf='11' tddis='1', tddis='0' tddis='1',
peb 3081 pef 3081 description of functional blocks data sheet 81 2000-09-27 preliminary 3.6.3 activation initiated by the network termination nt info 0 has to be transmitted as long as no valid info (info 2 or info 4) is received. after reception of info 2 or info 4 transmission of info 3 has to be started. data can be transmitted if info 4 has been received. figure 39 example of activation/deactivation initiated by the network termination (nt). activation/deactivation completely under software control note: rinf and xinf are receive- and transmit-infos of the registers tr_sta tr_cmd. act_deac_lt_ext_s.vsd rinf='01' rinf='10' xinf='011' info 0 info 2 info 3 info 4 rinf='11' t1 te info 0 info 0 info 0 t2 te t3 te xinf='000' rinf='00' te nt s/t interface c interface t1 te : 2 to 6 s/t frames (0.5 ms to 1.5 ms) t3 te : 4 s/t frames (1 ms) t2 te : 2 s/t frames (0.5 ms) tddis='1', tddis='0' tddis='1',
peb 3081 pef 3081 description of functional blocks data sheet 82 2000-09-27 preliminary 3.7 iom-2 interface the sbcx-x supports the iom-2 interface in linecard mode and in terminal mode with single clock and double clock. the iom-2 interface consists of four lines: fsc, dcl, dd and du. the rising edge of fsc indicates the start of an iom-2 frame. the dcl and the bcl clock signals synchronize the data transfer on both data lines du and dd. the dcl is twice the bit rate, the bcl rate is equal to the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle and sampled at the falling edge of the second clock cycle. the iom-2 interface can be enabled/disabled with the dis_iom bit in the iom_cr register. te mode a dcl signal and bcl signal (pin bcl/sclk) output is provided and the fsc signal is generated by the receive dpll which synchronizes it to the received s/t frame. the bcl clock together with the two serial data strobe signals (sds1, sds2) can be used to connect time slot oriented standard devices to the iom-2 interface. if the transceiver is disabled (tr_con.dis_tr) the dcl and fsc pins become input. in this case the clock mode bit (iom_cr.clkm) selects between a double clock and a single clock input for dcl. the clock rate/frequency of the iom-2 signals in te mode are: dd, du: 768 kbit/s fsc (o): 8 khz dcl (o): 1536 khz (double clock rate) bcl (o): 768 khz (single clock rate) option - transceiver disabled (dis_tr = ? 1 ? ): fsc (i): 8 khz dcl (i): 1536 ... 4096 khz, in steps of 512 khz (double clock rate) lt-s, lt-t, nt modes the iom-2 clock signals fsc and bcl are input. in lt-t mode a 1536 khz output clock synchronous to s is provided at pin sclk which can directly be connected to the dcl input. dd, du: data rate = dcl/2 kbit/s (lt-t mode) fsc (i): 8 khz dcl (i): 512 ... 4096 khz, in steps of 512 khz (double clock rate) sclk (o): 1536 khz (lt-t mode), bcl derived via dcl/2 (lt-s/nt mode) note: in all modes the direction of the data lines du and dd is not fix but depending on the timeslot which can be seen in the figures below.
peb 3081 pef 3081 description of functional blocks data sheet 83 2000-09-27 preliminary iom-2 frame structure (te mode) the frame structure on the iom-2 data ports (du, dd) of a master device in iom-2 terminal mode is shown in figure 40 . figure 40 iom ? -2 frame structure in terminal mode the frame is composed of three channels channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (mon0) and a command/indication channel (ci0) for control and programming of the layer-1 transceiver. channel 1 contains two 64-kbit/s intercommunication channels (ic) plus a monitor and command/indicate channel (mon1, ci1) to program or transfer data to other iom- 2 devices. channel 2 is used for the tlc-bus access. only the command/indicate bits are specified in this channel.
peb 3081 pef 3081 description of functional blocks data sheet 84 2000-09-27 preliminary iom-2 frame structure (lt-s, lt-t modes) this mode is used in lt-s and lt-t applications. the frame is a multiplex of up to eight iom-2 channels (dcl = 4096 khz, see figure 41 ), each of which has the structure described above. the reset value for assignment to one of the eight channels (0 to 7) is done via pin strapping (ch0-2), however the host can reprogram the selected timeslot in dch_tsdp.tss. figure 41 multiplexed frame structure of the iom-2 interface in non-te timing mode iom-2 frame structure (nt mode) in nt mode one iom-2 channel is used (dcl=512 khz). the channel structure is the same as described above. itd09635 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 b1 b2 monitor d c/i mm rx 125 fsc dcl dd du s iom ch0 iom ch0 r r
peb 3081 pef 3081 description of functional blocks data sheet 85 2000-09-27 preliminary 3.7.1 iom-2 handler the iom-2 handler offers a great flexibility for handling the data transfer between the different functional units of the sbcx-x and voice/data devices connected to the iom-2 interface. additionally it provides a microcontroller access to all timeslots of the iom-2 interface via the four controller data access registers (cda). figure 42 shows the architecture of the iom-2 handler. for illustrating the functional description it contains all configuration and control registers of the iom-2 handler. a detailed register description can be found in chapter 4.3 . the pcm data of the functional units transceiver (tr) and the controller data access (cda) can be configured by programming the time slot and data port selection registers (tsdp). with the tss bits (time slot selection) the pcm data of the functional units can be assigned to each of the 32 pcm time slots of the iom-2 frame. with the dps bit (data port selection) the output of each functional unit is assigned to du or dd respectively. the input is assigned vice versa. with the data control registers (xxx_cr) the access to the data of the functional units can be controlled by setting the corresponding control bits (en, swap). the iom-2 handler also provides access to the monitor channel (mon) c/i channels (c/i0, c/i1) and tic bus (tic) the access to these channels is controlled by the register mon_cr and dci_cr. the iom-2 interface with the two serial data strobes (sds1,2) is controlled by the control registers iom_cr, sds1_cr and sds2_cr. the reset configuration of the sbcx-x iom-2 handler corresponds to the defined frame structure and data ports of a master device in iom-2 terminal mode (see figure 40 ).
peb 3081 pef 3081 description of functional blocks data sheet 86 2000-09-27 preliminary . figure 42 architecture of the iom handler (example configuration) 3186_07 cda control ( dps, tss, en_tbm, swap, en_i1/0, en_o1/0, mcdaxy, stixy, stovxy, ackxy ) cda registers cda10 cda11 cda20 cda21 cda_tsdpxy cdax_crx mcda sti msti asti controller data access (cda) control monitor data (dps, cs2-0, en_mon) mon_cr tic bus disable (tic_dis) iom_cr dci_cr c/i1 (dps_ci1, en_ci1) control transceiver data access (dps, tss, cs2-0, en_d, en_b1r, en_b1x, en_b2r, en_b2x ) tr_tsdp_bc1 tr_tsdp_bc2 trc_cr d, b1, b2, c/i0 data c/i1 data c/i0 data tic bus data monitor data cda data transceiver data tr d-channel rx/tx b1-channel rx b1-channel tx mon handler tic data microcontroller interface iom_cr ( ens_tss, ens_tss+1, ens_tss+3, tss, sds_bcl iom-2 interface du dd fsc dcl bcl / sclk sds1 iom-2 handler c/i0 (cs2-0) dcic_cr b2-channel rx b2-channel tx sds1_cr en_bcl, clkm, dis_od, dis_iom, diom_inv, diom_sds note: the registers shown above are used to control the corresponding functional block (e.g. programming of timeslot, data port, enabling/disabling, etc.) c/i data control c/i0 c/i1 sds2 sds2_cr
peb 3081 pef 3081 description of functional blocks data sheet 87 2000-09-27 preliminary 3.7.1.1 controller data access (cda) with its four controller data access registers (cda10, cda11, cda20, cda21) the sbcx-x iom-2 handler provides a very flexible solution for the host access to up to 32 iom-2 time slots. the functional unit cda (controller data access) allows with its control and configuration registers looping of up to four independent pcm channels from du to dd or vice versa over the four cda registers shifting of two independent pcm channels to another two independent pcm channels on both data ports (du, dd). between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. if this is not the case a switching function is performed monitoring of up to four time slots on the iom-2 interface simultaneously microcontroller read and write access to each pcm timeslot the access principle which is identical for the two channel register pairs cda10/11 and cda20/21 is illustrated in figure 43 . each of the index variables x,y used in the following description can be 1 or 2 for x and 0 or 1 for y. the prefix ? cda_ ? from the register names has been omitted for simplification. to each of the four cdaxy data registers a tsdpxy register is assigned by which the time slot and the data port can be determined. with the tss (time slot selection) bits a time slot from 0...31 can be selected. with the dps (data port selection) bit the output of the cdaxy register can be assigned to du or dd respectively. the time slot and data port for the output of cdaxy is always defined by its own tsdpxy register. the input of cdaxy depends on the swap bit in the control registers crx. if the swap bit = ? 0 ? (swap is disabled) the time slot and data port for the input and output of the cdaxy register is defined by its own tsdpxy register. if the swap bit = ? 1 ? (swap is enabled) the input port and timeslot of the cdax0 is defined by the tsdp register of cdax1 and the input port and timeslot of cdax1 is defined by the tsdp register of cdax0. the input definition for timeslot and data port cdax0 are thus swapped to cdax1 and for cdax1 swapped to cdax0. the output timeslots are not affected by swap. the input and output of every cdaxy register can be enabled or disabled by setting the corresponding en (-able) bit in the control register cdax_cr. if the input of a register is disabled the output value in the register is retained. usually one input and one output of a functional unit (transceiver, hdlc controller, cda register) is programmed to a timeslot on iom-2 (e.g. for b-channel transmission in upstream direction the hdlc controller writes data onto iom and the transceiver reads data from iom). for monitoring data in such cases a cda register is programmed as described below under ? monitoring data ? . besides that none of the iom timeslots must be assigned more than one input and output of any functional unit.
peb 3081 pef 3081 description of functional blocks data sheet 88 2000-09-27 preliminary . figure 43 data access via cdax1 and cdax2 register pairs looping and shifting data figure 44 gives examples for typical configurations with the above explained control and configuration possibilities with the bits tss, dps, en and swap in the registers tsdpxy or cdax_cr: a) looping iom-2 time slot data from du to dd or vice versa (swap = 0) b) shifting data from tsa to tsb and tsc to tsd in both transmission directions (swap = 1) c) switching data from tsa to tsb and looping from du to dd or tsc to tsd and looping from dd to du respectively tsa is programmed in tsdp10, tsb in tsdp11, tsc in tsdp20 and tsd in tsdp21. it should also be noted that the input control of cda registers is swapped if swap=1 while the output control is not affected (e.g. for cda11 in example a: en_i1=1 and en_o1=1, whereas for cda11 in example b: en_i0=1 and en_o1=1). du cdax1 control register cda_crx dd 1 1 time slot selection (tss) input swap (swap) 1 x = 1 or 2; a,b = 0...31 data port cda_tsdpx1 0 1 0 1 iom_hand.fm4 1 0 1 1 enable input * (en_o0) output cda_tsdpx0 1 0 cdax0 1 (en_i0) (en_i1) input * enable output (en_o1) selection (dps) data port selection (dps) selection (tss) time slot tsa tsa tsb tsb *) in the normal mode (swap=0) the input of cdax0 and cdax1 is enabled via en_i0 and en_i1, respectively. if swap=1 en_i0 controls the input of cdax1 and en_i1 controls the input of cdax0. the output control (en_o0 and en_o1) is not affected by swap.
peb 3081 pef 3081 description of functional blocks data sheet 89 2000-09-27 preliminary figure 44 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) shifting and looping data tsa tsb tsc tsd cda10 cda11 cda20 cda21 tsa tsb tsc tsd du dd tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd b) shifting d ata a) looping data .tss: .dps .swap ? 0 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd c) s witching d ata tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 1 ?
peb 3081 pef 3081 description of functional blocks data sheet 90 2000-09-27 preliminary figure 45 shows the timing of looping tsa from du to dd (a = 0...31) via cdaxy register. tsa is read in the cdaxy register from du and is written one frame later on dd. . figure 45 data access when looping tsa from du to dd figure 46 shows the timing of shifting data from tsa to tsb on du (dd). in figure 46a) shifting is done in one frame because tsa and tsb didn ? t succeed direct one another (a, b = 0...29 and b a+2 . in figure 46b) shifting is done from one frame to the following frame. this is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). at looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). sti and stov are explained in the section ? synchronous transfer ? . if there is no controller intervention the looping and shifting is done autonomous. tsa du tsa fsc cdaxy c rd wr ack stov tsa dd tsa sti a = 0...31 *) if access by the c is required *)
peb 3081 pef 3081 description of functional blocks data sheet 91 2000-09-27 preliminary figure 46 data access when shifting tsa to tsb on du (dd) tsa du tsb fsc cdaxy c rd wr ack stov sti tsa sti tsa fsc cdaxy c rd wr ack stov sti tsb tsa tsb (dd) (a,b: 0...31 and (b = a+1 or b peb 3081 pef 3081 description of functional blocks data sheet 92 2000-09-27 preliminary monitoring data figure 47 gives an example for monitoring of two iom-2 time slots each on du or dd simultaneously. for monitoring on du and/or dd the channel registers with even numbers (cda10, cda20) are assigned to time slots with even numbers ts(2n) and the channel registers with odd numbers (cda11, cda21) are assigned to time slots with odd numbers ts(2n+1). the user has to take care of this restriction by programming the appropriate time slots. however, this rule is only valid if two blocks (e.g. transceiver and hdlc controller) are programmed to these timeslots and are communicating via iom-2. if only one block is programmed to this timeslot, the timeslots for cdax0 and cdax1 can programmed completely independently. . figure 47 example for monitoring data monitoring tic bus (te mode) monitoring the tic bus (ts11) is handled as a special case. the tic bus can be monitored with the registers cdax0 by setting the en_tbm (enable tic bus monitoring) bit in the control registers crx. in this special case the tsdpx0 must be set to 08 h for monitoring from du or 88 h for monitoring from dd respectively. by this it is possible to monitor the tic bus (ts11) and the odd numbered d-channel (ts3) simultaneously on du and dd. cda10 cda11 cda20 cda21 ts(2n) ts(2n+1) du dd tss: ts(2n) ts(2n+1) tss: ? 1 ? ? 1 ? dps: ? 0 ? ? 0 ? dps: ? 0 ? ? 0 ? en_o: ? 1 ? ? 1 ? en_i: ? 0 ? ? 0 ? en_o: ? 1 ? ? 1 ? en_i: cda_cr1. cda_cr2.
peb 3081 pef 3081 description of functional blocks data sheet 93 2000-09-27 preliminary synchronous transfer while looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). the microcontroller access to the cdaxy registers can be synchronized by means of four programmable synchronous transfer interrupts (stixy) and synchronous transfer overflow interrupts (stovxy) in the sti register. depending on the dps bit in the corresponding cda_tsdpxy register the stixy is generated two (for dps= ? 0 ? ) or one (for dps= ? 1 ? ) bcl clock after the selected time slot (cda_tsdpxy.tss). one bcl clock is equivalent to two dcl clocks. in the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (sti/stov) out of the four cda interrupt pairs (sti10/stov10, sti11/ stov11, sti20/stov20, sti21/stov21). an stovxy 0 is related to its stixy 0 and is only generated if stixy 0 is enabled and not acknowledged. however, if stixy 0 is masked, the stovxy 0 is generated for any other stixy 1 which is enabled and not acknowledged. table 9 gives some examples for that. it is assumed that an stov interrupt is only generated because an sti interrupt was not acknowledged before. in example 1 only the stixy 0 is enabled and thus stixy 0 is only generated. if no sti is enabled, no interrupt will be generated even if stov is enabled (example 2). in example 3 stixy 0 is enabled and generated and the corresponding stovxy 0 is disabled. stixy 1 is disabled but its stovxy 1 is enabled, and therefore stovxy 1 is generated due to stixy 0 . in example 4 additionally the corresponding stovxy 0 is enabled, so stovxy 0 and stovxy 1 are both generated due to stixy 0 . in example 5 additionally the stixy 1 is enabled with the result that stovxy 0 is only generated due to stixy 0 and stovxy 1 is only generated due to stixy 1 . compared to the previous example stovxy 0 is disabled in example 6, so stovxy 0 is not generated and stovxy 1 is only generated for stixy 1 but not for stixy 0 . compared to example 5 in example 7 a third stovxy 2 is enabled and thus stovxy2 is generated additionally for both stixy 0 and stixy 1 .
peb 3081 pef 3081 description of functional blocks data sheet 94 2000-09-27 preliminary an stov interrupt is not generated if all stimulating sti interrupts are acknowledged. an stixy must be acknowledged by setting the ackxy bit in the asti register until two bcl clocks (for dps= ? 0 ? ) or one bcl clocks (for dps= ? 1 ? ) before the time slot which is selected for the appropriate stixy. the interrupt structure of the synchronous transfer is shown in figure 48 . . figure 48 interrupt structure of the synchronous data transfer table 9 examples for synchronous transfer interrupts enabled interrupts (register msti) generated interrupts (register sti) sti stov sti stov xy 0 -xy 0 -example 1 -xy 0 - - example 2 xy 0 xy 1 xy 0 xy 1 example 3 xy 0 xy 0 ; xy 1 xy 0 xy 0 ; xy 1 example 4 xy 0 ; xy 1 xy 0 ; xy 1 xy 0 xy 1 xy 0 xy 1 example 5 xy 0 ; xy 1 xy 1 xy 0 xy 1 - xy 1 example 6 xy 0 ; xy 1 xy 0 ; xy 1 ; xy 2 xy 0 xy 1 xy 0 ; xy 2 xy 1 ; xy 2 example 7 sti11 msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 ack11 asti ack10 ack20 ack21 st mos tran wov interrupt ista mask mos tran wov st cic cic
peb 3081 pef 3081 description of functional blocks data sheet 95 2000-09-27 preliminary figure 49 shows some examples based on the timeslot structure. figure a) shows at which point in time an sti and stov interrrupt is generated for a specific timeslot. figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. . figure 49 examples for the synchronous transfer interrupt control with one enabled stixy xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 a) interrupts for data access to time slot 0 (b1 after reset), msti.sti10 and msti.stov10 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '1' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 b) interrupts for data access to time slot 0 (b1 after reset), stov interrupt used as flag for "intermediate cda access"; msti.sti10 and msti.stov21 enabled c) interrupts for data access to time slot 0 and 5, msti.sti10, msti.stov10, msti.sti21 and msti.stov21 enabled sti_stov.vsd xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '0' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 d) interrupts for data access to time slot 0 (b1 after reset), stov21 interrupt used as flag for "intermiediate cda access", stov10 interrupt used as flag for "cda access failed"; msti.sti10, msti.stov10 and msti.stov21 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 : stov interrupt generated for a not acknowledged sti interrupt : sti interrupt generated
peb 3081 pef 3081 description of functional blocks data sheet 96 2000-09-27 preliminary 3.7.2 serial data strobe signal and strobed data clock for time slot oriented standard devices connected to the iom-2 interface the sbcx-x provides two independent data strobe signals sds1 and sds2. instead of a data strobe signal a strobed iom-2 bit clock can be provided on pin sds1 and sds2. 3.7.2.1 serial data strobe signal the two strobe signals can be generated with every 8-khz frame and are controlled by the registers sds1/2_cr. by programming the tss bits and three enable bits (ens_tss, ens_tss+1, ens_tss+3) a data strobe can be generated for the iom-2 time slots ts, ts+1 and ts+3 and any combination of them. the data strobes for ts and ts+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for ts+3 is always 2 bits long (bit7, bit6). figure 50 shows three examples for the generation of a strobe signal. in example 1 the sds is active during channel b2 on iom-2 whereas in the second example during ic2 and mon1. the third example shows a strobe signal for 2b+d channels which can be used e.g. for an idsl (144kbit/s) transmission.
peb 3081 pef 3081 description of functional blocks data sheet 97 2000-09-27 preliminary figure 50 data strobe signal fsc dd,du m r m x d ci0 sds1,2 (example1) sds1,2 (example2) sds1,2 (example3) tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' = '0' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' = '1' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 3: = '0 h ' = '1' = '1' = '1' ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 strobe.vsd for all examples sds_conf.sds1/2_bcl must be set to ? 0 ? .
peb 3081 pef 3081 description of functional blocks data sheet 98 2000-09-27 preliminary 3.7.2.2 strobed iom-2 bit clock the strobed iom-2 bit clock is active during the programmed window. outside the programmed window a ? 0 ? is driven. two examples are shown in figure 51 . figure 51 strobed iom-2 bit clock. register sds_conf programmed to 01 h the strobed bit clock can be enabled in sds_conf.sds1/2_bcl. fsc dd,du m r m x d ci0 sds1 (example1) sds1 (example2) ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 bcl_strobed.vsd tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' = '0' = '0' = '1' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' = '1' = '1' = '0' setting of sds1_cr: for all examples sds_conf.sds1_bcl must be set to ? 1 ? .
peb 3081 pef 3081 description of functional blocks data sheet 99 2000-09-27 preliminary 3.7.3 iom-2 monitor channel the iom-2 monitor channel (see figure 52 ) is utilized for information exchange in the monitor channel between a master mode device and a slave mode device. the montior channel data can be controlled by the bits in the monitor control register (mon_cr). for the transmission of the monitor data one of the iom-2 channels (3 iom-2 channels in te mode, 8 channels in non te mode) can be selected by setting the monitor channel selection bits (mcs) in the monitor control register (mon_cr). the dps bit in the same register selects between an output on du or dd respectively and with en_mon the monitor data can be enabled/disabled. the default value is monitor channel 0 (mon0) enabled and transmission on dd. figure 52 examples of monitor channel applications in iom-2 te mode the monitor channel of the sbcx-x can be used in following applications which are illustrated in figure 52 : as a master device the sbcx-x can program and control other devices attached to the iom-2 which do not need a parallel microcontroller interface e.g. arcofi-ba psb 2161. this facilitates redesigning existing terminal designs in which e.g. an interface of an expansion slot is realized with iom-2 interface and monitor programming. 3086_08 monitor handler layer 1 v/d module (e.g. arcofi-ba) iom-2 monitor channel c monitor handler layer 1 v/d module (e.g. isar34) iom-2 monitor channel c master device monitor handler layer 1 v/d module (e.g. isar34) iom-2 monitor channel c data exchange between two c systems c slave device
peb 3081 pef 3081 description of functional blocks data sheet 100 2000-09-27 preliminary as a slave device the transceiver part of the sbcx-x is programmed and controlled from a master device on iom-2 (e.g. isar34 psb 7115). this is used in applications where no microcontroller is connected directly to the sbcx-x in order to simplify host interface connection. the hdlc controlling is processed by the master device therefore the hdlc data is transferred via iom-2 interface directly to the master device. for data exchange between two microcontroller systems attached to two different devices on one iom-2 backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between the two systems. this simplifies the system design of terminal equipment. 3.7.3.1 handshake procedure the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync (fsc), the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted once per 8-khz frame until the transfer is acknowledged via the mr bit. the monitor channel protocol is described in the following section and figure 53 illustrates this. the relevant control and status bits for transmission and reception are listed in table 10 and table 11 . table 10 transmit direction control/ status bit register bit function control mocr mxc mx bit control mie transmit interrupt enable status mosr mda data acknowledged mab data abort msta mac transmission active table 11 receive direction control/ status bit register bit function control mocr mrc mr bit control mre receive interrupt enable status mosr mdr data received mer end of reception
peb 3081 pef 3081 description of functional blocks data sheet 101 2000-09-27 preliminary figure 53 monitor channel protocol (iom-2) itd10032 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mie = 1 mox = adr mxc = 1 mac = 1 mox = data1 mda int. mda int. mda int. mxc = 0 mdr int. rd mor (=adr) mrc = 1 mdr int. mdr int. mrc = 0 mer int. p p 125 s rd mor (=data1) rd mor (=data2) mox = data2 mac = 0
peb 3081 pef 3081 description of functional blocks data sheet 102 2000-09-27 preliminary before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a ? 0 ? in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to ? 1 ? . this enables the mx bit to go active ( ? 0 ? ), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates an mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to ? 1 ? to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor interrupt enable (mie) to ? 1 ? . as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to ? 0 ? . this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mda interrupt status. this "mda interrupt ? write data ? mdr interrupt ? read data ? mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to ? 0 ? . this enforces an inactive ( ? 1 ? ) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to ? 0 ? . during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to ? 0 ? . an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter.
peb 3081 pef 3081 description of functional blocks data sheet 103 2000-09-27 preliminary the monitor transfer protocol rules are summarized in the following section: a pair of mx and mr in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission . a start of a transmission is initiated by the transmitter by setting the mxc bit to ? 1 ? enabling the internal mx control. the receiver acknowledges the received first byte by setting the mr control bit to ? 1 ? enabling the internal mr control. the internal mx,mr control indicates or acknowledges a new byte in the mon slot by toggling mx,mr from the active to the inactive state for one frame. two frames with the mr-bit set to inactive indicate a receiver request for abort . the transmitter can delay a transmission sequence by sending the same byte continuously. in that case the mx-bit remains active in the iom-2 frame following the first byte occurrence. delaying a transmission sequence is only possible while the receiver mr-bit and the transmitter mx-bit are active. since a double last-look criterion is implemented the receiver is able to receive the mon slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. to control this handshake procedure a collision detection mechanism is implemented in the transmitter. this is done by making a collision check per bit on the transmitted monitor data and the mx bit. monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. two frames with the mx bit in the inactive state indicates the end of a message (eom). transmission and reception of monitor messages can be performed simultaneously. this feature is used by the sbcx-x to send back the response before the transmission from the controller is completed (the sbcx-x does not wait for eom from controller). 3.7.3.2 error treatment in case the sbcx-x does not detect identical monitor messages in two successive frames, transmission is not aborted. instead the sbcx-x will wait until two identical bytes are received in succession. a transmission is aborted of the sbcx-x if an error in the mr handshaking occurs a collision on the iom-2 bus of the monitor data or mx bit occurs the transmission time-out timer expires a reception is aborted by the device if an error in the mx handshaking occurs or an abort request from the opposite device occurs
peb 3081 pef 3081 description of functional blocks data sheet 104 2000-09-27 preliminary mx/mr treatment in error case in the master mode the mx/mr bits are under control of the microcontroller through mxc or mrc, respectively. an abort is indicated by an mab interrupt or mer interrupt, respectively. in the slave mode the mx/mr bits are under control of the device. an abort is always indicated by setting the mx/mr bit inactive for two or more iom-2 frames. the controller must react with eom. figure 54 shows an example for an abort requested by the receiver, figure 55 shows an example for an abort requested by the transmitter and figure 56 shows an example for a successful transmission. figure 54 monitor channel, transmission abort requested by the receiver figure 55 monitor channel, transmission abort requested by the transmitter mx (du) iom -2 frame no. 1 2 345 67 eom mr (dd) 1 0 1 0 mon_rec-abort.vsd abort request from receiver mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_tx-abort.vsd abort request from transmitter
peb 3081 pef 3081 description of functional blocks data sheet 105 2000-09-27 preliminary figure 56 monitor channel, normal end of transmission 3.7.3.3 monitor channel programming as a master device as a master device the sbcx-x can program and control other devices attached to the iom-2 interface. the master mode is selected by default if the serial control interface (sci) is used by the host. the monitor data is written by the microprocessor in the mox register and transmitted via iom-2 dd (du) line to the programmed/controlled device e.g. arcofi-ba psb 2161 or iec-q te psb 21911. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter chapter 3.7.3.1 . if the transmitted command was a read command the slave device responds by sending the requested data. the data structure of the transmitted monitor message depends on the device which is programmed. therefore the first byte of the message is a specific address code which contains in the higher nibble a monitor channel address to identify different devices. the length of the messages depends on the accessed device and the type of monitor command. mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_norm.vsd 8
peb 3081 pef 3081 description of functional blocks data sheet 106 2000-09-27 preliminary 3.7.3.4 monitor channel programming as a slave device in applications without direct host controller connection the sbcx-x must operate in the monitor slave mode which can be selected by pinstrapping the microcontroller interface pins according table 3 respectively in chapter 3.2 . as a slave device the transceiver part of the sbcx-x is programmed and controlled by a master device at the iom-2 interface. all programming data required by the sbcx-x is received in the monitor time slot on the iom-2 and is transferred in the mor register. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter 3.7.3.1 . the first byte of the monitor message must contain in the higher nibble the monitor channel address code which is ? 1010 ? for the sbcx-x. the lower nibble distinguishes between a programming command or an identification command. identification command in order to be able to identify unambiguously different hardware designs of the sbcx-x by software, the following identification command is used: the sbcx-x responds to this dd identification sequence by sending a du identification sequence: design: six bit code, specific for each device in order to identify differences in operation e.g. 000001 sbcx-x peb 3081 version 1.3 this identification sequence is usually done once, when the terminal is connected for the first time. this function is used so that the software can distinguish between different possible hardware configurations. however this sequence is not compulsory. dd 1st byte value 10100000 dd 2nd byte value 00000000 du 1st byte value 10100000 du 2nd byte value 0 1 design
peb 3081 pef 3081 description of functional blocks data sheet 107 2000-09-27 preliminary programming sequence the programming sequence is characterized by a ? 1 ? being sent in the lower nibble of the received address code. the data structure after this first byte and the principle of a read/ write access to a register is similar to the structure of the serial control interface described in chapter 3.2.2 . for write access the header 43 h /47 h can be used and for read access the header 40 h /44 h . all registers can be read back when setting the r/w bit in the byte for the command/ register address. the sbcx-x responds by sending its iom-2 specific address byte (a1 h ) followed by the requested data. 3.7.3.5 monitor time-out procedure to prevent lock-up situations in a monitor transmission a time-out procedure can be enabled by setting the time-out bit (tout) in the monitor configuration register (mconf). an internal timer is always started when the transmitter must wait for the reply of the addressed device. after 5 ms without reply the timer expires and the transmission will be aborted with a eom (end of message) command by setting the mx bit to ? 1 ? for two consecutive iom-2 frames. dd 1st byte value 10100001 dd 2nd byte value header byte dd 3rd byte value r/w register address dd 4th byte value data 1 dd (nth + 3) byte value data n
peb 3081 pef 3081 description of functional blocks data sheet 108 2000-09-27 preliminary 3.7.3.6 monitor interrupt logic figure 57 shows the monitor interrupt structure of the sbcx-x. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable ( mre ) and mr bit control ( mrc ). the monitor channel end of reception mer , monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie . mre prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is active (1) but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. (additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol.) figure 57 monitor interrupt structure st mos tran wov interrupt ista mask st mos tran wov mre mdr mie mda mer mab mosr mocr cic cic
peb 3081 pef 3081 description of functional blocks data sheet 109 2000-09-27 preliminary 3.7.4 c/i channel handling the command/indication channel carries real-time status information between the sbcx-x and another device connected to the iom-2 interface. one c/i channel (called c/i0) conveys the commands and indications between the layer-1 and the c/i handler of the sbcx-x. it can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. c/i0 channel access may be arbitrated via the tic bus access protocol. in this case the arbitration is done in iom-2 channel 2 (see figure 40 ). the c/i0 channel is accessed via register cir0 (in receive direction, layer-1 to layer- 2) and register cix0 (in transmit direction, layer-2 to layer-1). the c/i0 code is four bits long. a listing and explanation of the layer-1 c/i codes can be found in chapter 3.5.4 . in the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ista.cic). a new code must be found in two consecutive iom-2 frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix0 is continuously transmitted in c/i0. a second c/i channel (called c/i1) can be used to convey real time status information between the sbcx-x and various non-layer-1 peripheral devices e.g. psb 2161 arcofi-ba. the c/i1 channel consists of four or six bits in each direction.the width can be changed from 4bit to 6bit by setting bit cix1.cicw. in 4-bit mode 6-bits are written whereby the higher 2 bits must be set to ? 1 ? and 6-bits are read whereby only the 4 lsbs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). the c/i1 channel is accessed via registers cir1 and cix1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. cic interrupt logic figure 58 shows the cic interrupt structure. a cic interrupt may originate ? from a change in received c/i channel 0 code (cic0) or ? from a change in received c/i channel 1 code (cic 1).
peb 3081 pef 3081 description of functional blocks data sheet 110 2000-09-27 preliminary the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e in the cix1 register. in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. the cir0 is buffered with a fifo size of two. if a second code change occurs in the received c/i channel 0 before the first one has been read, immediately after reading of cir0 a new interrupt will be generated and the new code will be stored in cir0. if several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. for cir1 no fifo is available. the actual code of the received c/i channel 1 is always stored in cir1. figure 58 cic interrupt structure 3.7.5 d-channel access control d-channel access control is defined to guarantee all connected tes and hdlc controllers a fair chance to transmit data in the d-channel. collisions are possible on the iom-2 interface if there is more than one hdlc controller connected or on the s-interface when there is more than one terminal connected in a point to multipoint configuration (nt te1 ? te8). both arbitration mechanisms are implemented in the sbcx-x and will be described in the following two chapters. st mos tran cic wov interrupt ista mask cic1 ci1e cic0 cir0 cix1 mos tran wov st cic
peb 3081 pef 3081 description of functional blocks data sheet 111 2000-09-27 preliminary 3.7.5.1 tic bus d-channel access control the tic bus is imlemented to organize the access to the layer-1 functions provided in the sbcx-x (c/i-channel) and to the d-channel from up to 7 external communication controllers ( figure 59 ). to this effect the outputs of the d-channel controllers (e.g. icc - isdn communication controller peb 2070) are wired-or (negative logic, i.e. a ? 0 ? wins) and connected to pin du. the inputs of the iccs are connected to pin dd. external pull-up resistors on du/ dd are required. the arbitration mechanism must be activated by setting tr_mode2.dim2-0=00x. figure 59 applications of tic bus in iom-2 bus configuration the arbitration mechanism is implemented in the last octet in iom-2 channel 2 of the iom-2 interface ( figure 60 ). an access request to the tic bus may either be generated by software via a p access to the c/i channel or by one of the d-channel controllers (icc). a software access request to the bus is effected by setting the bac bit (cix0 register) to ? 1 ? . 3081_09 icc (7) icc (2) icc (1) . . . sbcx-x nt tic-bus on iom-2 s-interface u-interface icc
peb 3081 pef 3081 description of functional blocks data sheet 112 2000-09-27 preliminary in the case of an access request to the c/i channel, the sbcx-x checks the bus accessed-bit bac (bit 5 of last octet of ch2 on du, see figure 60 ) for the status "bus free ? , which is indicated by a logical ? 1 ? . if the bus is free, the sbcx-x transmits its individual tic bus address tad. the sbcx-x sends its tic bus address tad and compares it bit by bit with the value on du. if a sent bit set to ? 1 ? is read back as ? 0 ? because of the access of another source with a lower tad wishing access to d- or c/i- channel, the sbcx-x withdraws immediately from the tic bus, i.e. the remaining tad bits are not transmitted. the tic bus is occupied by the device which sends its address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. this one will set bac=0 on tic bus and starts d- channel transmission in the same frame. figure 60 structure of last octet of ch2 on du when the tic bus is seized by the icc, the bus is identified to other devices as occupied via the du ch2 bus accessed-bit state ? 0 ? until the access request is withdrawn. after a successful bus access, the icc is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. if none of the devices connected to the iom-2 interface request access to the d and c/ i channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. du
peb 3081 pef 3081 description of functional blocks data sheet 113 2000-09-27 preliminary 3.7.5.2 s-bus priority mechanism for d-channel the s-bus access procedure specified in itu i.430 was defined to organize d-channel access with multiple tes connected to a single s-bus ( figure 62 ). to implement collision detection the d (channel) and e (echo) bits are used. the d- channel s-bus condition is indicated towards the iom-2 interface with the s/g bit, i.e. the availability of the s/t interface d channel is indicated in bit 5 "stop/go" (s/g) of the dd last octet of ch2 channel ( figure 61 ). s/g = 1 : stop s/g = 0 : go figure 61 structure of last octet of ch2 on dd the stop/go bit is available to other layer-2 devices connected to the iom-2 interface to determine if they can access the s/t bus d channel. the access to the d-channel is controlled by a priority mechanism which ensures that all competing tes are given a fair access chance. this priority mechanism discriminates among the kind of information exchanged and information exchange history: layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). furthermore, once a te having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. the te is given back its normal level within a priority class when all tes have had an opportunity to transmit information at the normal level of that priority class. the priority mechanism is based on a rather simple method: a te not transmitting layer- 2 frames sends binary 1s on the d-channel. as layer-2 frames are delimited by flags consisting of the binary pattern ? 01111110 ? and zero bit insertion is used to prevent flag imitation, the d-channel may be considered idle if more than seven consecutive 1s are detected on the d-channel. hence by monitoring the d echo channel, the te may determine if the d-channel is currently used by another te or not. itd09693 d ci1 mon1 ic2 ic1 ci0 mon0 b2 b1 mr mx mx mr s/g a/b a/b s/g stop/go available/blocked dd e e
peb 3081 pef 3081 description of functional blocks data sheet 114 2000-09-27 preliminary a te may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. this number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. a te, when in the active condition, is monitoring the d echo channel, counting the number of consecutive binary 1s. if a 0 bit is detected, the te restarts counting the number of consecutive binary 1s. if the required number of 1s according to the actual level of priority has been detected, the te may start transmission of an hdlc frame. if a collision occurs, the te immediately shall cease transmission, return to the d-channel monitoring state, and send 1s over the d-channel. figure 62 d-channel access control on the s-interface 3081_10 d-channel control sbcx-x peb 3081 nt s-interface d-bits e-bits u-interface . . . te 1 te 2 te 8 d-channel control sbcx-x peb 3081 d-channel control sbcx-x peb 3081
peb 3081 pef 3081 description of functional blocks data sheet 115 2000-09-27 preliminary s-bus d-channel access control in the sbcx-x the above described priority mechanism is fully implemented in the sbcx-x. for this purpose the d-channel collision detection according to itu i.430 must be enabled by setting tr_mode2.dim2-0 to ? 0x1 ? . in this case the transceiver continuously compares the received e-echo bits with its own transmitted d data bits. depending on the priority class selected, 8 (priority 8) or 10 (priority 10) consecutive ones (high priority level) need to be detected before the transceiver sends valid d- channel data on the upstream d-bits on s. in low priority level 9 (priority 8) or 11 (priority 10) consecutive ones are required. the priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the command/indication (c/i) channel of the iom-2 interface to the transceiver. if the activation is initiated by a te, the priority class is selected implicitly by the choice of the activation command. if the s-interface is activated from the nt, an activation command selecting the desired priority class should be programmed at the te on reception of the activation indication (ai8 or ai10). in the activated state the priority class may be changed whenever required by simply programming the desired activation request command (ar8 or ar10). 3.7.5.3 s-bus d-channel control in lt-t if the te frame structure on the iom-2 interface is selected, the same d-channel access procedures as described in chapter 3.7.5.2 are used in lt-t mode. for other frame structures used in lt-t mode, d-channel access on s is handled similarly, with the difference that the s/g bit is not available on iom-2 but only on the s/g bit output pin (sgo). 3.7.5.4 d-channel control in the intelligent nt (tic- and s-bus) in intelligent nt applications (selected via register tr_mode.mode2-0) one or more d-channel controllers on the iom-2 interface share the upstream d-channel with all connected tes on the s interface. the transceiver incorporates an elaborate statemachine for d-channel priority handling on iom-2. for the access to the d-channel a similar arbitration mechanism as on the s interface (writing d-bits, reading back e-bits) is performed for all d-channel sources on iom-2. due to this an equal and fair access is guaranteed for all d-channel sources on both the s interface and the iom-2 interface. this arbitration mechanism is only available in iom-2 te mode (12 pcm timeslots) per frame with enabled tic bus. the access to the upstream d-channel is handled via the s/g bit for the hdlc controllers and via e-bit for all connected terminals on s (e-bits are inverted to block the terminals on s). furthermore, if more than one hdlc source is requesting d-channel access on iom-2 the tic bus mechanism is used.
peb 3081 pef 3081 description of functional blocks data sheet 116 2000-09-27 preliminary the arbiter permanently counts the ? 1s ? in the upstream d-channel on iom-2. if the necessary number of ? 1s ? is counted and an hdlc controller on iom-2 requests upstream d-channel access (bac bit is set to 0), the arbiter allows this d-channel controller immediate access and blocks other tes on s (e-bits are inverted). similar as on the s-interface the priority for d-channel access on iom-2 can be configured to 8 or 10 (tr_cmd.dprio). the upstream device can stop all d-channel sources by setting the a/b-bit to 0. the s/ g bit is not evaluated in this mode. the configuration settings of the sbcx-x in intelligent nt applications are summarized in table 12 . note: for mode selection in the tr_mode register the mode1/2 bits are used to select intelligent nt mode, mode0 selects nt or lt-s state machine. with the configuration settings shown above the sbcx-x in intelligent nt applications provides for equal access to the d-channel for terminals connected to the s-interface and for d-channel sources on iom-2. for a detailed understanding the following sections provide a complete description on the procedures used by the d-channel priority handler on iom-2, although it may not be necessary to study that in order to use this mode. table 12 sbcx-x configuration settings in intelligent nt applications configuration description configuration setting select intelligent nt mode transceiver mode register: tr_mode.mode0 = 0 (nt state machine) or tr_mode.mode0 = 1 (lt-s state machine) tr_mode.mode1 = 1 tr_mode.mode2 = 1 enable s/g bit evaluation transceiver mode register 2: tr_mode2.dim2-0 = 001
peb 3081 pef 3081 description of functional blocks data sheet 117 2000-09-27 preliminary 1. nt d-channel controller transmits upstream in the initial state ( ? ready ? state) neither the local d-channel sources on iom-2 nor any of the terminals connected to the s-bus transmit in the d-channel. the sbcx-x s-transceiver thus receives bac = ? 1 ? (iom-2 du line) and transmits s/g = ? 1 ? (iom-2 dd line). the access will then be established according to the following procedure: local d-channel source verifies that bac bit is set to one (currently no bus access). local d-channel source issues tic bus address and verifies that no controller with higher priority requests transmission (tic bus access must always be performed even if no other d-channel sources are connected to iom-2). local d-channel source issues bac = ? 0 ? to block other sources on iom-2 and to announce d-channel access. sbcx-x s-transceiver pulls s/g bit to zero ( ? idle ? state) as soon as n d-bits = ? 1 ? are counted on iom-2 (see note) to allow for further d-channel access. sbcx-x s-transceiver transmits inverted echo channel (e bits) on the s-bus to block all connected s-bus terminals (e = d ). local d-channel source commences with d data transmission on iom-2 as long as it receives s/g = ? 0 ? . after d-channel data transmission is completed the controller sets the bac bit to one. sbcx-x s-transceiver transmits non-inverted echo (e = d). sbcx-x s-transceiver pulls s/g bit to one ( ? ready ? state) to block the d-channel controller on iom-2. note: ? local d-channel source ? means any d-channel source on the iom-2 interface. right after transmission the s/g bit is pulled to ? 1 ? until n successive d-bits = ? 1 ? occur on the iom-2 interface. as soon as n d-bits = ? 1 ? are seen, the s/g bit is set to ? 0 ? and the sbcx-x d-channel controller may start transmission again (if tic bus is occupied). this allows an equal access for d-channel sources on iom-2 and on the s interface. the number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). figure 63 illustrates the signal flow in an intelligent nt and the algorithm of the d- channel priority handler on iom-2 implemented in the sbcx-x.
peb 3081 pef 3081 description of functional blocks data sheet 118 2000-09-27 preliminary 2. terminal transmits d-channel data upstream the initial state is identical to that described in the last paragraph. when one of the connected s-bus terminals needs to transmit in the d-channel, access is established according to the following procedure: sbcx-x s-transceiver (in intelligent nt) recognizes that the d-channel on the s-bus is active. sbcx-x s-transceiver transfers s-bus d-channel data transparently through to the upstream iom-2 bus (iom-2 channel 0). for both cases described above the exchange indicates via the a/b bit (controlled by layer 1) that d-channel transmission on this line is permitted (a/b = ? 1 ? ). data transmission could temporarily be prohibited by the exchange when only a single d-channel controller handles more lines (a/b = ? 0 ? , elic-concept). in case the exchange prohibits d data transmission on this line the a/b bit is set to ? 0 ? (block). for u pn applications with s extension this forces the intelligent nt sbcx-x s- transceiver to transmit an inverted echo channel on the s-bus, thus disabling all terminal requests, and switches s/g to a/b , which blocks the d-channel controller in the intelligent nt. note: although the sbcx-x s-transceiver operates in lt-s mode and is pinstrapped to iom-2 channel 0 or 1 it will write into iom-2 channel 2 at the s/g bit position. figure 63 data flow for collision resolution procedure in intelligent nt sbcx-x d-channel controller 1 (te mode timing) u transceiver iom-2 masterdevice, e.g. iec-q te du dd d d d s/g bac d s/g a/b bac tba d s d-channel e-channel te te te exchange d iom 3081_03 d-channel controller 2 (e.g. icc peb2070)
peb 3081 pef 3081 description of functional blocks data sheet 119 2000-09-27 preliminary 3.7.6 activation/deactivation of iom-2 interface the iom-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. in this deactivated state is fsc = ? 1 ? , dcl and bcl = ? 0 ? and the data lines are ? 1 ? . the iom-2 interface can be kept active while the s interface is deactivated by setting the cfs bit to "0" (mode1 register). this is the case after a hardware reset. if the iom-2 interface should be switched off while the s interface is deactivated, the cfs bit should be set to ? 1 ? . in this case the internal oscillator is disabled when no signal (info 0) is present on the s bus and the c/i command is ? 1111 ? = diu. if the te wants to activate the line, it has first to activate the iom-2 interface either by using the "software power up" function (iom_cr.spu bit) or by setting the cfs bit to "0" again. the deactivation procedure is shown in figure 64 . after detecting the code diu (deactivate indication upstream) the layer 1 of the sbcx-x responds by transmitting did (deactivate indication downstream) during subsequent frames and stops the timing signals synchronously with the end of the last c/i (c/i0) channel bit of the fourth frame. figure 64 deactivation of the iom-2 interface the clock pulses will be enabled again when the du line is pulled low (bit spu in the iom_cr register), i.e. the c/i command tim = "0000" is received by layer 1, or when a non-zero level on the s-line interface is detected (if tr_conf0.ldd=0). the clocks are turned on after approximately 0.2 to 4 ms depending on the oscillator. iom ? -2 deactivated dc dc dc dc di di di di di di di di di b1 b2 d cio d cio dcl dd du fsc iom ? -2 itd09655_s.vsd dr dr dr dr dr
peb 3081 pef 3081 description of functional blocks data sheet 120 2000-09-27 preliminary dcl is activated such that its first rising edge occurs with the beginning of the bit following the c/i (c/i0) channel. after the clocks have been enabled this is indicated by the pu code in the c/i channel and, consequently, by a cic interrupt. the du line may be released by resetting the software power up bit iom_cr.spu = ? 0 ? and the c/i code written to cix0 before (e.g. tim or ar8) is output on du. the sbcx-x supplies iom-2 timing signals as long as there is no diu command in the c/i (c/i0) channel. if timing signals are no longer required and activation is not yet requested, this is indicated by programming diu in the cix0 register. figure 65 activation of the iom-2 interface itd09656 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ fsc du dd fsc du dd dcl spu = 1 spu = 0 cic : cixo = tim int. tim pu b1 b1 mx mr 0.2 to 4 ms 132 x dcl tim tim pu pu pu pu r iom -ch1 r iom -ch2 iom -ch2 r iom r -ch1 note: the value ? 132 x dcl ? is only valid for iom configurations with 3 iom channels.
peb 3081 pef 3081 description of functional blocks data sheet 121 2000-09-27 preliminary asynchronous awake (lt-s, nt, int. nt mode) the transceiver is in power down mode (deactivated state) and mode1.cfs=1 (tr_conf0.ldd is don ? t care in this case). due to any signal on the line the level detect circuit will asynchronously pull the du line on iom-2 to ? 0 ? which is deactivated again after 2 ms if the oscillator is fully operational. if the oscillator is just starting up in operational mode, the 2 ms duration is extended correspondingly.
peb 3081 pef 3081 description of functional blocks data sheet 122 2000-09-27 preliminary 3.8 auxiliary interface the aux interface provides various functions, which depend on the operation mode (te, lt-t, lt-s, nt or intelligent nt mode) selected by pins mode0 and mode1/eaw (see table 13 ). after reset the pins are switched as inputs until further configuration is done by the host. general purpose i/o aux0-2 (te, int. nt mode) these pins can be used as programmable i/o lines. as inputs (aoe.oex=1) the state at the pin is latched in when the host performes read operation to register arx. as outputs (aoe.oex=0) the value in register atx is driven on the pins with a minimum delay after the write operation to this register is performed. they can be configured as open drain (acfg1.odx=0) or push/pull outputs (acfg1.odx=1). the status ( ? 1 ? or ? 0 ? ) at output pins can be read back from register arx, which may be different from the atx value, e.g. if another device drives a different level. channel select ch0-2 (lt-t, lt-s, nt mode) in linecard mode one fsc frame is a multiplex of up to eight iom-2 channels, each of them consisting of b1-, b2-, monitor-, d- and c/i-channel and mr- and mx-bits. one of eight channels on the iom-2 interface is selected by ch0-2. these pins must be strapped to vdd or vss according to table 14 . table 13 aux pin functions pin te, int. nt mode lt-t, lt-s, nt mode aux0 aux0 (i/o) ch0 (i) aux1 aux1 (i/o) ch1 (i) aux2 aux2 (i/o) ch2 (i)
peb 3081 pef 3081 description of functional blocks data sheet 123 2000-09-27 preliminary for dcl = 1.536 mhz one of the iom-2 channels 0 - 2 can be selected, for dcl = 4.096 mhz any of the eight iom-2 channels can be selected. the channel select pins have direct effect on the timeslot selection of the following registers: tr_tsdp_bc1 tr_tsdp_bc2 tr_cr, trc_cr dci_cr, dcic_cr mon_cr table 14 iom-2 channel selection ch2 ch1 ch0 channel on iom-2 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
peb 3081 pef 3081 detailed register description data sheet 124 2000-09-27 preliminary 4 detailed register description the register mapping of the sbcx-x is shown in figure 66 . figure 66 register mapping of the sbcx-x the register set ranging from 22 h -3f h pertains to the transceiver and c/i-channel handler registers. 3081_04 (not used) iom-2 and monitor handler (not used) *1) 40h 22h 70h ffh transceiver, c/i handler 60h interrupt, general configuration 00h
peb 3081 pef 3081 detailed register description data sheet 125 2000-09-27 preliminary the address range from 40 h -5b h is assigned to the iom handler with the registers for timeslot and data port selection (tsdp) and the control registers (cr) for the transceiver data (tr), monitor data (mon), c/i data (ci) and controller access data (cda), serial data strobe signal (sds), iom interface (iom) and synchronous transfer interrupt (sti). the address range from 5c h -5f h pertains to the monitor handler. general interrupt and configuration registers are contained in the address range 60 h -65 h . the register summaries of the sbcx-x are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (read/write). a detailed register description follows these register summaries. the register summaries and the description are sorted in ascending order of the register address.
peb 3081 pef 3081 detailed register description data sheet 126 2000-09-27 preliminary transceiver, c/i-channel handler, auxiliary interface name76543210addrr/wres reserved 00 h - 21 h tr_ mode2 00000dim2dim1dim022 h r/w 00 h reserved 23-2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h tr_ conf0 dis_ tr bus en_ icv 0 l1sw 0 exlp ldd 30 h r/w 01h tr_ conf1 0rpll_ adj en_ sfsc 00xx x31 h r/w tr_ conf2 dis_ tx pds 0 rlp 0 0 sgp sgd 32 h r/w 80 h tr_sta rinf slip icv 0 fsyn 0 ld 33 h r00 h tr_cmd xinf dprio tddis pd lp_a 0 34 h r/w 08 h sqrr1 msyn mfen 0 0 sqr11sqr12sqr13sqr14 35 h r40 h sqxr1 0 mfen 0 0 sqx11sqx12sqx13 sqx14 35 h w4f h sqrr2 sqr21sqr22sqr23sqr24sqr31sqr32sqr33sqr34 36 h r00 h sqxr2 sqx21sqx22sqx23sqx24sqx31sqx32sqx33 sqx34 36 h w00 h sqrr3 sqr41sqr42sqr43sqr44sqr51sqr52sqr53sqr54 37 h r00 h sqxr3 sqx41sqx42sqx43sqx44sqx51sqx52sqx53 sqx54 37 h w00 h istatr 0 x x x ld ric sqc sqw 38 h r00 h
peb 3081 pef 3081 detailed register description data sheet 127 2000-09-27 preliminary masktr1111ldricsqcsqw39 h r/w ff h tr_ mode 0000 dch_ inh mode 2 mode 1 mode 0 3a h r/w 00 h reserved 3b h acfg100000od2od1od03c h r/w 00 h acfg20000aclled003d h r/w 00 h aoe 11111oe2oe1oe03e h r/w ff h arx -----ar2ar1ar03f h r atx 00000at2at1at03f h w00 h transceiver, c/i-channel handler, auxiliary interface name76543210addrr/wres
peb 3081 pef 3081 detailed register description data sheet 128 2000-09-27 preliminary iom handler (timeslot , data port selection, cda data and cda control register) name76543210addrr/wres cda10 controller data access register (ch10) 40 h r/w ff h cda11 controller data access register (ch11) 41 h r/w ff h cda20 controller data access register (ch20) 42 h r/w ff h cda21 controller data access register (ch21) 43 h r/w ff h cda_ tsdp10 dps 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 tss 47 h r/w 81 h reserved 48-4b h tr_ tsdp_ bc1 dps 0 0 tss 4c h r/w 00 h tr_ tsdp_ bc2 dps 0 0 tss 4dh r/w 01 h cda1_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4e h r/w 00 h cda2_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4f h r/w 00 h
peb 3081 pef 3081 detailed register description data sheet 129 2000-09-27 preliminary iom handler (control registers, synchronous transfer interrupt control), monitor handler name 76543210addrr/wres tr_cr (ci_cs=0) en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 50 h r/w f8 h trc_cr (ci_cs=1) 00000 cs2-0 50 h r/w 00 h reserved 51-52 h dci_cr (ci_cs=0) dps_ ci1 en_ ci1 00000053 h r/w 80 h dcic_cr (ci_cs=1) 00000 cs2-0 53 h r/w 00 h mon_cr dps en_ mon 000 cs2-0 54 h r/w 40 h sds1_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 55 h r/w 00 h sds2_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 56 h r/w 00 h iom_cr spu dis_ aw ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom 57 h r/w 08 h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0 0 0 0 ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h sds_ conf 0000diom_ inv diom_ sds sds2_ bcl sds1_ bcl 5a h r/w 00 h mcda mcda21 mcda20 mcda11 mcda10 5b h rff h
peb 3081 pef 3081 detailed register description data sheet 130 2000-09-27 preliminary mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosrmdrmermdamab00005d h r00 h mocrmremrcmiemxc00005e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h
peb 3081 pef 3081 detailed register description data sheet 131 2000-09-27 preliminary interrupt, general configuration registers name76543210addrr/wres ista 0 0 st cic aux tran mos 0 60 h r00 h mask 1 1 st cic aux tran mos 1 60 h wff h auxi 0 0 eaw wov tin 0 0 0 61 h r00 h auxm 1 1 eaw wov tin 1 1 1 61 h wff h mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 62 h r/w 00 h mode20000int_ pol 0 0 ppsdx 63 h r/w 00 h id 0 0 design 64 h r01 h sres res_ ci 00res_ mon 0res_ iom res_ tr res_ rsto 64 h w00 h timr tmd 0 cnt 65 h r/w 00 h reserved 66 h - 6f h
peb 3081 pef 3081 detailed register description data sheet 132 2000-09-27 preliminary 4.1 transceiver and c/i registers 4.1.1 tr_mode2 - transceiver mode register 2 value after reset: 00 h dim2-0 ... digital interface modes these bits define the characteristics of the iom data ports (du, dd). the dim0 bit enables/disables the collission detection. the dim1 bit enables/disables the tic bus access. the effect of the individual dim bits is summarized in the table below . example: ? 010 ? selects transparent d-channel, collision detection disabled and tic bus disabled. 70 tr_ mode2 0 0 0 0 0 dim2 dim1 dim0 rd/wr (22) dim2 dim1 dim0 characteristics 0 0 transparent d-channel, the collission detection is disabled 0 1 stop/go bit evaluated for d-channel access handling 0 0 last octet of iom channel 2 used for tic bus access 0 1 tic bus access is disabled 1 x x reserved
peb 3081 pef 3081 detailed register description data sheet 133 2000-09-27 preliminary 4.1.2 cir0 - command/indication receive 0 value after reset: f3 h codr0 ... c/i code 0 receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 ... c/i code 0 change a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. cic1 ... c/i code 1 change a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. s/g ... stop/go bit monitoring indicates the availability of the upstream d-channel on the s/t interface. 1: stop 0: go bas ... bus access status indicates the state of the tic-bus: 0: the sbcx-x itself occupies the d- and c/i-channel 1: another device occupies the d- and c/i-channel note: the codr0 bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code is made available in cir0 at the first and second read of that register, respectively. 70 cir0 codr0 cic0 cic1 s/g bas rd (2e)
peb 3081 pef 3081 detailed register description data sheet 134 2000-09-27 preliminary 4.1.3 cix0 - command/indication transmit 0 value after reset: fe h codx0 ... c/i-code 0 transmit code to be transmitted in the c/i-channel 0. the code is only transmitted if the tic bus is occupied. if tic bus is enabled but occupied by another device, only ? 1s ? are transmitted. tba2-0 ... tic bus address defines the individual address for the sbcx-x on the iom bus. this address is used to access the c/i- and d-channel on the iom interface. note: if only one device is liable to transmit in the c/i- and d-channels of the iom it should always be given the address value ? 7 ? . bac ... bus access control only valid if the tic-bus feature is enabled (moded.dim2-0). if this bit is set, the sbcx-x will try to access the tic-bus to occupy the c/i-channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the sbcx-x with tic-bus address (tba2- 0, stcr register) ? 7 ? , which has the lowest priority in a bus configuration. 4.1.4 cir1 - command/indication receive 1 value after reset: fe h codr1 ... c/i-code 1 receive cicw, ci1e ... c/i-channel width, c/i-channel 1 interrupt enable these two bits contain the read back values from cix1 register (see below). 70 cix0 codx0 tba2 tba1 tba0 bac wr (2e) 70 cir1 codr1 cicw ci1e rd (2f)
peb 3081 pef 3081 detailed register description data sheet 135 2000-09-27 preliminary 4.1.5 cix1 - command/indication transmit 1 value after reset: fe h codx1 ... c/i-code 1 transmit bits 7-2 of c/i-channel 1 timeslot. cicw... c/i-channel width cicw selects between a 4 bit ( ? 0 ? ) and 6 bit ( ? 1 ? ) c/i1 channel width. the c/i1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. however in write direction the full codx1 code is transmitted, i.e. the host must write the higher two bits to ? 1 ? . ci1e ... c/i-channel 1 interrupt enable interrupt generation ista.cic of cir0.cic1 is enabled (1) or masked (0). 4.1.6 tr_conf0 - transceiver configuration register 0 value after reset: 01 h dis_tr ... disable transceiver setting dis_tr to ? 1 ? disables the transceiver. in order to reenable the transceiver again, a transceiver reset must be issued (sres.res_tr = 1). the transceiver must not be reenabled by setting dis_tr from ? 1 ? to ? 0 ? . for general information please refer to chapter 3.3.9 . bus ... point-to-point / bus selection (nt/lt-s/int. nt mode only) 0: adaptive timing (point-to-point, extended passive bus). 1: fixed timing (short passive bus). 70 cix1 codx1 cicw ci1e wr (2f) 70 tr_ conf0 dis_ tr bus en_ icv 0 l1sw 0 exlp ldd rd/wr (30)
peb 3081 pef 3081 detailed register description data sheet 136 2000-09-27 preliminary en_icv ... enable illegal code violation 0: normal operation 1: icv enabled. the receipt of at least one illegal code violation within one multiframe is indicated by the c/i indication ? 1011 ? (cvr) in two consecutive iom frames. l1sw ... enable layer 1 state machine in software 0: layer 1 state machine of the sbcx-x is used 1: layer 1 state machine is disabled. the functionality can be realized in software. the commands can be written to register tr_cmd and the status can be read from tr_sta. for general information please refer to chapter 3.5 . exlp ... external loop in case the analog loopback is activated with c/i = arl or with the lp_a bit in the tr_cmd register the loop is a 0: internal loop next to the line pins 1: external loop which has to be closed between sr1/2 and sx1/sx2 note:the external loop is only useful if bit dis_tx of register tr_conf2 is set to ? 0 ? . for general information please refer to chapter 3.3.10 . ldd ... level detection discard 0: automatic clock generation after detection of any signal on the line in power down state 1: no clock generation after detection of any signal on the line in power down state note: if an interrupt by the level detect circuitry is generated, the microcontroller has to set this bit to ? 0 ? for an activation of the s/t interface. for general information please refer to chapter 3.3.8 and chapter 3.7.6 .
peb 3081 pef 3081 detailed register description data sheet 137 2000-09-27 preliminary 4.1.7 tr_conf1 - transceiver configuration register 1 value after reset: 0x h rpll_adj ... receive pll adjustment 0: dpll tracking step is 0.5 xtal period per s-frame 1: dpll tracking step is 1 xtal period per s-frame en_sfsc ... enable short fsc 0: no short fsc is generated 1: a short fsc is generated once per multiframe (every 40th iom frame) x ... undefined the value of these bits depends on the selected mode. it is important to note that these bits must not be overwritten to a different value when accessing this register. 4.1.8 tr_conf2 - transmitter configuration register 2 value after reset: 80 h dis_tx ... disable line driver 0: transmitter is enabled 1: transmitter is disabled for general information please refer to chapter 3.3.9 . 70 tr_ conf1 0rpll_ adj en_ sfsc 0 0 x x x rd/wr (31) 70 tr_ conf2 dis_ tx pds 0 rlp 0 0 sgp sgd rd/wr (32)
peb 3081 pef 3081 detailed register description data sheet 138 2000-09-27 preliminary pds ... phase deviation select defines the phase deviation of the s-transmitter. 0: the phase deviation is 2 s-bits minus 7 oscillator periods plus analog delay plus delay of the external circuitry. 1: the phase deviation is 2 s-bits minus 9 oscillator periods plus analog delay plus delay of the external circuitry. for general information please refer to chapter 3.3.7 . rlp ... remote line loop 0: remote line loop open 1: remote line loop closed for general information please refer to chapter 3.3.10 . sgp ... stop/go bit polarity defines the polarity of the s/g bit output on pin sgo. 0: low active (sgo=0 means ? go ? ; sgo=1 means ? stop ? ) 1: high active (sgo=1 means ? go ? ; sgo=0 means ? stop ? ) sgd ... stop/go bit duration defines the duration of the s/g bit output on pin sgo. 0: active during the d-channel timeslot 1: active during the whole corresponding iom frame (starts and ends with the beginning of the d-channel timeslot) note: outside the active window of sgo (defined in sgd) the level on pin sgo remains in the ? stop ? -state depending on the selected polarity (sgp), i.e. sgo=1 (if sgp=0) or sgo=0 (if sgp=1) outside the active window.
peb 3081 pef 3081 detailed register description data sheet 139 2000-09-27 preliminary 4.1.9 tr_sta - transceiver status register value after reset: 00 h important: this register is used only if the layer 1 state machine of the sbcx-x is disabled (tr_conf0.l1sw = 1) and implemented in software! with the sbcx-x layer 1 state machine enabled, the signals from this register are automatically evaluated. for general information please refer to chapter 3.5 . rinf ... receiver info 00: received info 0 01: received any signal except info 1 - 4 10: received info 1 (nt mode) or info 2 (te mode) 11: received info 3 (nt mode) or info 4 (te mode) slip ... slip detected a ? 1 ? in this bit position indicates that a slip is detected in the receive or transmit path. icv ... illegal code violation 0: no illegal code violation is detected 1: illegal code violation (ansi t1.605) in data stream is detected fsyn ... frame synchronization state 0: the s/t receiver is not synchronized 1: the s/t receiver has synchronized to the framing bit f ld ... level detection 0: no receive signal has been detected on the line. 1: any receive signal has been detected on the line. 70 tr_ sta rinf slip icv 0 fsyn 0 ld rd (33)
peb 3081 pef 3081 detailed register description data sheet 140 2000-09-27 preliminary 4.1.10 tr_cmd - transceiver command register value after reset: 08 h important: this register is only writable if the layer 1 state machine of the sbcx-x is disabled (tr_conf0.l1sw = 1)! with the sbcx-x layer 1 state machine enabled, the signals from this register are automatically generated, but nevertheless this register can always be read. dprio can also be written in intelligent nt mode. xinf ... transmit info 000: transmit info 0 001: reserved 010: transmit info 1 (te mode) or info 2 (nt mode) 011: transmit info 3 (te mode) or info 4 (nt mode) 100: send continous pulses at 192 kbit/s alternating or 96 khz rectangular, respectively (scp) 101: send single pulses at 4 kbit/s with alternating polarity corresponding to 2 khz fundamental mode (ssp) 11x: reserved dprio ... d-channel priority (always writable in int. nt mode) 0: priority class 1 for d channel access on iom (int. nt) or on s interface (te/lt-t) 1: priority class 2 for d channel access on iom (int. nt) or on s interface (te/lt-t) tddis ... transmit data disabled (te mode) 0: the b and d channel data are transparently transmitted on the s/t interface if info 3 is being transmitted 1: the b and d channel data are set to logical ? 1 ? on the s/t interface if info 3 is being transmitted pd ... power down 0: the transceiver is set to operational mode 1: the transceiver is set to power down mode for general information please refer to chapter 3.5.1.2 . 70 tr_ cmd xinf dprio tddis pd lp_a 0 rd/wr (34)
peb 3081 pef 3081 detailed register description data sheet 141 2000-09-27 preliminary lp_a ... loop analog the setting of this bit corresponds to the c/i command arl. 0: analog loop is open 1: analog loop is closed internally or externally according to the exlp bit in the tr_conf0 register for general information please refer to chapter 3.3.10 . 4.1.11 sqrr1 - s/q-channel receive register 1 value after reset: 40 h for general information please refer to chapter 3.3.2 . msyn ... multiframe synchronization state 0: the s/t receiver has not synchronized to the received f a and m bits 1: the s/t receiver has synchronized to the received f a and m bits mfen ... multiframe enable read-back of the mfen bit of the sqxr register sqr11-14 ... received s bits received s bits in frames 1, 6, 11 and 16 (te mode) received q bits in frames 1, 6, 11 and 16 (nt mode). 70 sqrr msyn mfen 0 0 sqr11 sqr12 sqr13 sqr14 rd (35)
peb 3081 pef 3081 detailed register description data sheet 142 2000-09-27 preliminary 4.1.12 sqxr1- s/q-channel tx register 1 value after reset: 4f h mfen ... multiframe enable used to enable or disable the multiframe structure (see chapter 3.3.2 ) 0: s/t multiframe is disabled 1: s/t multiframe is enabled readback value in sqrr1. sqx11-14 ... transmitted s/q bits transmitted q bits (f a bit position) in frames 1, 6, 11 and 16 (te mode), transmitted s bits (f a bit position) in frames 1, 6, 11 and 16 (nt mode). 4.1.13 sqrr2 - s/q-channel receive register 2 value after reset: 00 h sqr21-24, sqr31-34... received s bits (te mode only) received s bits in frames 2, 7, 12 and 17 (sqr21-24, subchannel 2), and in frames 3, 8, 13 and 18 (sqr31-34, subchannel 3). 70 sqxr1 0 mfen 0 0 sqx11 sqx12 sqx13 sqx14 wr (35) 70 sqrr2 sqr21 sqr22 sqr23 sqr24 sqr31 sqr32 sqr33 sqr34 rd (36)
peb 3081 pef 3081 detailed register description data sheet 143 2000-09-27 preliminary 4.1.14 sqxr2 - s/q-channel tx register 2 value after reset: 00 h sqx21-24, sqx31-34... transmitted s bits (nt mode only) transmitted s bits in frames 2, 7, 12 and 17 (sqx21-24, subchannel 2), and in frames 3, 8, 13 and 18 (sqx31-34, subchannel 3). 4.1.15 sqrr3 - s/q-channel receive register 3 value after reset: 00 h sqr41-44, sqr51-54... received s bits (te mode only) received s bits in frames 4, 9, 14 and 19 (sqr41-44, subchannel 4), and in frames 5, 10, 15 and 20 (sqr51-54, subchannel 5). 4.1.16 sqxr3 - s/q-channel tx register 3 value after reset: 00 h sqx41-44, sqx51-54... transmitted s bits (nt mode only) transmitted s bits in frames 4, 9, 14 and 19 (sqx41-44, subchannel 4), and in frames 5, 10, 15 and 20 (sqx51-54, subchannel 5). 70 sqxr2 sqx21 sqx22 sqx23 sqx24 sqx31 sqx32 sqx33 sqx34 wr (36) 70 sqrr3 sqr41 sqr42 sqr43 sqr44 sqr51 sqr52 sqr53 sqr54 rd (37) 70 sqxr3 sqx41 sqx42 sqx43 sqx44 sqx51 sqx52 sqx53 sqx54 wr (37)
peb 3081 pef 3081 detailed register description data sheet 144 2000-09-27 preliminary 4.1.17 istatr - interrupt status register transceiver value after reset: 00 h for all interrupts in the istatr register the following logical states are defined: 0: interrupt is not acitvated 1: interrupt is acitvated x ... reserved bits set to ? 1 ? in this bit position must be ignored. ld ... level detection any receive signal has been detected on the line. this bit is set to ? 1 ? (i.e. an interrupt is generated if not masked) as long as any receiver signal is detected on the line. ric ... receiver info change ric is activated if one of the tr_sta bits rinf or icv has changed. this bit is reset by reading the tr_sta register. sqc ... s/q-channel change a change in the received s-channel (te) or q-channel (nt) has been detected. the new code can be read from the sqrxx bits of registers sqrr1-3 within the duration of the next multiframe (5 ms). this bit is reset by a read access to the corresponding sqrrx register. sqw ... s/q-channel writable the s/q channel data for the next multiframe is writable. the register for the q (s) bits to be transmitted (received) has to be written (read) within the duration of the next multiframe (5 ms). this bit is reset by writing register sqxrx. 70 istatr 0 x x x ld ric sqc sqw rd (38)
peb 3081 pef 3081 detailed register description data sheet 145 2000-09-27 preliminary 4.1.18 masktr - mask transceiver interrupt value after reset: ff h the transceiver interrupts ld, ric, sqc and sqw are enabled (0) or disabled (1). 4.1.19 tr_mode - transceiver mode register 1 value after reset: 000000xx b for general information please refer also to chapter 3.7.5.4 . dch_inh ... d-channel inhibit (nt, lt-s, int. nt mode only) setting this bit to ? 1 ? has the effect that the s-transceiver blocks the access to the d- channel on s by inverting the e-bits. the pin dci, which performs the same funtion, is internally combined (exor-logic) with dch_inh, i.e. either setting the bit to ? 1 ? or pulling the pin high will block the d-channel access, however activating pin and bit simultaneously must not be done. if this bit was not set before, reading dch_inh reflects the status on pin dci, i.e. the d- channel inhibit function is controlled by the pin. if the function should be controlled by programming dch_inh, the pin dci must be strapped to ? 0 ? or ? 1 ? . 70 masktr 1 1 1 1 ld ric sqc sqw rd/wr (39) 70 tr_ mode 0 0 0 0 dch_ inh mode 2 mode 1 mode 0 rd/wr (3a)
peb 3081 pef 3081 detailed register description data sheet 146 2000-09-27 preliminary mode2-0 ... transceiver mode 000: te mode 001: lt-t mode 010: nt mode 011: lt-s mode 110: intelligent nt mode (with nt state machine) 111: intelligent nt mode (with lt-s state machine) 100: reserved 101: reserved note: the three modes te, lt-t and lt-s can be selected by pin strapping (reset values for bits tr_mode.mode0,1 loaded from pins mode0,1), all other modes are programmable only.
peb 3081 pef 3081 detailed register description data sheet 147 2000-09-27 preliminary 4.2 auxiliary interface registers 4.2.1 acfg1 - auxiliary configuration register 1 value after reset: 00 h for general information please refer to chapter 3.8 . od2-0 ... output driver select for aux2 - aux0 0: output is open drain 1: output is push/pull note: the odx configuration is only valid if the corresponding output is enabled in the aoe register. aux0-2 are only available in te and int. nt mode and not in all other modes (used as channel select). 4.2.2 acfg2 - auxiliary configuration register 2 value after reset: 00 h acl ... acl function select 0: pin acl automatically indicates the s-bus activation status by a low level. 1: the output state of acl is programmable by the host in bit led. note: an led with preresistance may directly be connected to acl . led ... led control if enabled (acl=1) the led with preresistance connected between vdd and acl is switched ... 0: off (high level on pin acl ) 1: on (low level on pin acl ) 70 acfg1 0 0 0 0 0 od2 od1 od0 rd/wr (3c) 70 acfg2 0 0 0 0 acl led 0 0 rd/wr (3d)
peb 3081 pef 3081 detailed register description data sheet 148 2000-09-27 preliminary 4.2.3 aoe - auxiliary output enable register value after reset: ff h for general information please refer to chapter 3.8 . oe2-0 ... output enable for aux2 - aux0 0: pin aux2-0 is configured as output. the value of the corresponding bit in the atx register is driven on aux2-0. 1: pin aux2-0 is configured as input. the value of the corresponding bit can be read from the arx register. note: in nt and lt modes the pins aux0-2 are not available as i/o pins. 4.2.4 arx - auxiliary interface receive register value after reset: (not defined) ar2-0 ... auxiliary receive the value of ar2-0 always reflects the level at pin aux2-0 at the time when arx is read by the host even if a pin is configured as output. note: in nt and lt modes the pins aux0-2 are not available as i/o pins. 70 aoe 1 1 1 1 1 oe2 oe1 oe0 rd/wr (3e) 70 arx -----ar2ar1ar0 rd (3f)
peb 3081 pef 3081 detailed register description data sheet 149 2000-09-27 preliminary 4.2.5 atx - auxiliary interface transmit register value after reset: 00 h at2-0 ... auxiliary transmit a ? 0 ? or ? 1 ? in at2-0 will drive a low or a high level at pin aux2-0 if the corresponding output is enabled in the aoe register. note: in nt and lt modes the pins aux0-2 are not available as i/o pins. 70 atx 0 0 0 0 0 at2 at1 at0 wr (3f)
peb 3081 pef 3081 detailed register description data sheet 150 2000-09-27 preliminary 4.3 iom-2 and monitor handler 4.3.1 cdaxy - controller data access register xy data registers cdaxy which can be accessed from the controller. 70 cdaxy controller data access register rd/wr (40-43) register register address value after reset cda10 40 h ff h cda11 41 h ff h cda20 42 h ff h cda21 43 h ff h
peb 3081 pef 3081 detailed register description data sheet 151 2000-09-27 preliminary 4.3.2 xxx_tsdpxy - time slot and data port selection for chxy this register determines the time slots and the data ports on the iom-2 interface for the data channels ? xy ? of the functional units ? xxx ? which are controller data access (cda) and transceiver (tr). the position of b-channel data from the s-interface is programmed in tr_tsdp_bc1 and tr_tsdp_bc2. dps ... data port selection 0:the data channel xy of the functional unit xxx is output on dd. the data channel xy of the functional unit xxx is input from du. 1:the data channel xy of the functional unit xxx is output on du. the data channel xy of the functional unit xxx is input from dd. note: for the cda (controller data access) data the input is determined by the cda_crx.swap bit. if swap = ? 0 ? the input for the cdaxy data is vice versa to the output setting for cdaxy. if the swap = ? 1 ? the input from cdax0 is vice versa to the output setting of cdax1 and the input from cdax1 is vice versa to the output setting of cdax0. see controller data access description in chapter 3.7.1.1 . tss ... timeslot selection selects one of 32 timeslots (0...31) on the iom-2 interface for the data channels. note: the reset values for tr_tsdp_bc1/2 are depending on the mode selection (mode0/1) and channel selection (ch0-2). 70 xxx_ tsdpxy dps 0 0 tss rd/wr (44-4d) register register address value after reset cda_tsdp10 44 h 00 h ( = output on b1-dd) cda_tsdp11 45 h 01 h ( = output on b2-dd) cda_tsdp20 46 h 80 h ( = output on b1-du) cda_tsdp21 47 h 81 h ( = output on b2-du) tr_tsdp_bc1 4c h 00 h ( = transceiver output on b1-dd), see note tr_tsdp_bc2 4d h 01 h ( = transceiver output on b2-dd), see note
peb 3081 pef 3081 detailed register description data sheet 152 2000-09-27 preliminary 4.3.3 cdax_cr - control register controller data access ch1x for general information please refer to chapter 3.7.1.1 . en_tbm ... enable tic bus monitoring 0: the tic bus monitoring is disabled 1: the tic bus monitoring with the cdax0 register is enabled. the tsdpx0 register must be set to 08 h for monitoring from du or 88 h for monitoring from dd, respectively. (this selection is only valid if iom_cr.tic_dis = 0). en_i1, en_i0 ... enable input cdax0, cdax1 0: the input of the cdax0, cdax1 register is disabled 1: the input of the cdax0, cdax1 register is enabled en_o1, en_o0 ... enable output cdax0, cdax1 0: the output of the cdax0, cdax1 register is disabled 1: the output of the cdax0, cdax1 register is enabled swap ... swap inputs 0: the time slot and data port for the input of the cdaxy register is defined by its own tsdpxy register. the data port for the cdaxy input is vice versa to the output setting for cdaxy. 1: the input (time slot and data port) of the cdax0 is defined by the tsdp register of cdax1 and the input of cdax1 is defined by the tsdp register of cdax0. the data port for the cdax0 input is vice versa to the output setting for cdax1. the data port for the cdax1 input is vice versa to the output setting for cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 to cdax0. the outputs are not affected by the swap bit. 70 cdax_ cr 00en_ tbm en_i1 en_i0 en_o1 en_o0 swap rd/wr (4e-4f) register register address value after reset cda1_cr 4e h 00 h cda2_cr 4f h 00 h
peb 3081 pef 3081 detailed register description data sheet 153 2000-09-27 preliminary 4.3.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) value after reset: f8 h read and write access to this register is only possible if iom_cr.ci_cs = 0. en_d ... enable transceiver d-channel data en_b2r ... enable transceiver b2 receive data en_b1r ... enable transceiver b1 receive data en_b2x ... enable transceiver b2 transmit data en_b1x ... enable transceiver b1 transmit data this register is used to individually enable/disable the d-channel (both rx and tx direction) and the receive/transmit paths for the b-channels of the s-transceiver. 0: the corresponding data path to the transceiver is disabled. 1: the corresponding data path to the transceiver is enabled. note: ? receive data ? refers to the data which is received on the s interface and forwarded to iom-2. ? transmit data ? refers to the data which is coming from iom-2 and transmitted on the s interface. cs2-0 ... channel select for transceiver d-channel this register is used to select one of eight iom channels to which the transceiver d- channel data is related to. note: the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. it should be noted that writing tr_cr.cs2-0 will also write to trc_cr.cs2-0 and therefore modify the channel selection for the transceiver c/i0 data. 70 tr_cr en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 rd/wr (50)
peb 3081 pef 3081 detailed register description data sheet 154 2000-09-27 preliminary 4.3.5 trc_cr - control register transceiver c/i0 (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. cs2-0 ... channel select for the transceiver c/i0 channel this register is used to select one of eight iom channels to which the transceiver c/i0 channel data is related to. the reset value is determined by the channel select pins ch2- 0 and the mode2-bit. 4.3.6 dci_cr - control register for ci1 handler (iom_cr.ci_cs=0) value after reset: 80 h read and write access to this register is only possible if iom_cr.ci_cs = 0. it should be noted that a writing the dci_cr register will also perform a write access to dcic_cr, i.e. the lower 3 bits of dci_cr will be written to dcic_cr.cs2-0. dps_ci1 ... data port selection ci1 handler data 0: the ci1 handler data is output on dd and input from du 1: the ci1 handler data is output on du and input from dd en_ci1 ... enable ci1 handler data 0: ci1 handler data access is disabled 1: ci1 handler data access is enabled note: the timeslot for the c/i1 handler cannot be programmed but is fixed to iom channel 1. 70 trc_cr 0 0 0 0 0 cs2-0 rd/wr (50) 70 dci_cr dps_ ci1 en_ ci1 000000rd/wr (53)
peb 3081 pef 3081 detailed register description data sheet 155 2000-09-27 preliminary 4.3.7 dcic_cr - control register for ci0 handler (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. cs2-0 ... channel select for c/i0 handler this register is used to select one of eight iom channels. if enabled, the data of the c/i0 handler is connected to the corresponding c/i0 timeslot of that iom channel. the reset value is determined by the channel select pins ch2-0 which are mapped to cs2-0. 70 dcic_cr 0 0 0 0 0 cs2-0 rd/wr (53)
peb 3081 pef 3081 detailed register description data sheet 156 2000-09-27 preliminary 4.3.8 mon_cr - control register monitor data value after reset: 40 h for general information please refer to chapter 3.7.3 . dps ... data port selection 0: the monitor data is output on dd and input from du 1: the monitor data is output on du and input from dd en_mon ... enable output 0: the monitor data input and output is disabled 1: the monitor data input and output is enabled cs2-0 ... monitor channel selection 000: the monitor data is input/output on mon0 (3rd timeslot on iom-2) 001: the monitor data is input/output on mon1 (7th timeslot on iom-2) 010: the monitor data is input/output on mon2 (11th timeslot on iom-2) : 111: the monitor data is input/output on mon7 (31st timeslot on iom-2) note: the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. 70 mon_cr dps en_ mon 0 0 0 cs2-0 rd/wr (54)
peb 3081 pef 3081 detailed register description data sheet 157 2000-09-27 preliminary 4.3.9 sdsx_cr - control register serial data strobe x value after reset: 00 h this register is used to select position and length of the strobe signals. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). for general information please refer to chapter 3.7.2 and chapter 3.7.2.2 . ens_tss ... enable serial data strobe of timeslot tss ens_tss+1 ... enable serial data strobe of timeslot tss+1 0: the serial data strobe signal sdsx is inactive during tss, tss+1 1: the serial data strobe signal sdsx is active during tss, tss+1 ens_tss+3 ... enable serial data strobe of timeslot tss+3 (d-channel) 0: the serial data strobe signal sdsx is inactive during the d-channel (bit7, 6) of tss+3 1: the serial data strobe signal sdsx is active during the d-channel (bit7, 6) of tss+3 tss ... timeslot selection selects one of 32 timeslots on the iom-2 interface (with respect to fsc) during which sdsx is active high or provides a strobed bcl clock output (see sds_conf.sds1/ 2_bcl). the data strobe signal allows standard data devices to access a programmable channel. 70 sdsx_cr ens_ tss ens_ tss+1 ens_ tss+3 tss rd/wr (55-56) register register address value after reset sds1_cr 55 h 00 h sds2_cr 56 h 00 h
peb 3081 pef 3081 detailed register description data sheet 158 2000-09-27 preliminary 4.3.10 iom_cr - control register iom data value after reset: 08 h spu ... software power up 0: the du line is normally used for transmitting data 1: setting this bit to ? 1 ? will pull the du line to low. this will enforce connected layer 1 devices to deliver iom-clocking. after a subsequent ista.cic-interrupt (c/i-code change) and reception of the c/i-code ? pu ? (power up indication in te-mode) the microcontroller writes an ar or tim command as c/i-code in the cix0-register, resets the spu bit and waits for the following cic-interrupt. for general information please refer to chapter 3.7.6 . dis_aw ... disable asynchronous awake (for nt, lt-s and int. nt mode) setting this bit to ? 1 ? disables the asynchronous awake function of the transceiver. ci_cs ... c/i channel selection the channel selection for d-channel and c/i-channel is done in the channel select bits ch2-0 of register tr_cr (for the transceiver) and dci_cr (for the c/i-channel controller). 0: a write access to cs2-0 has effect on the configuration of d- and c/i-channel, whereas a read access delivers the d-channel configuration only. 1: a write access to cs2-0 has effect on the configuration of the c/i-channel only, whereas a read access delivers the c/i-channel configuration only. tic_dis ... tic bus disable 0: the last octet of iom channel 2 (12th timeslot) is used as tic bus (in a frame timing mode with 12 timeslots only). 1: the tic bus is disabled. the last octet of the last iom time slot (ts 11) can be used as every time slot. 70 iom_cr spu dis_ aw ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom rd/wr (57)
peb 3081 pef 3081 detailed register description data sheet 159 2000-09-27 preliminary en_bcl ... enable bit clock bcl/sclk 0: the bcl/sclk clock is disabled 1: the bcl/sclk clock is enabled. clkm ... clock mode if the transceiver is disabled (dis_tr = ? 1 ? ) or in nt, lt-s and int. nt mode the dcl from the iom-2 interface is an input. 0: a double bit clock is connected to dcl 1: a single bit clock is connected to dcl for general information please refer to chapter 3.7 . dis_od ... disable open drain drivers 0: du/dd are open drain drivers 1: du/dd are push pull drivers dis_iom ... disable iom dis_iom should be set to ? 1 ? if external devices connected to the iom interface should be ? disconnected ? e.g. for power saving purposes or for not disturbing the internal iom connection. however, the sbcx-x internal operation is independent of the dis_iom bit. 0: the iom interface is enabled 1: the iom interface is disabled. the fsc, dcl clock outputs have high impedance; clock inputs are active; du, dd data line inputs are switched off and outputs have high impedance; except in te/lt-t mode the du line is input ( ? 0 ? -level causes activation), so the du pin must be terminated (pull up resistor).
peb 3081 pef 3081 detailed register description data sheet 160 2000-09-27 preliminary 4.3.11 sti - synchronous transfer interrupt value after reset: 00 h for all interrupts in the sti register the following logical states are applied: 0: interrupt is not activated 1: interrupt is activated the interrupts are automatically reset by reading the sti register. for general information please refer to chapter 3.7.1.1 . stovxy ... synchronous transfer overflow interrupt enabled stov interrupts for a certain stixy interrupt are generated when the stixy has not been acknowledged in time via the ackxy bit in the asti register. this must be one (for dps= ? 0 ? ) or zero (for dps= ? 1 ? ) bcl clocks before the time slot which is selected for the stov. stixy ... synchronous transfer interrupt depending on the dps bit in the corresponding tsdpxy register the synchronous transfer interrupt stixy is generated two (for dps= ? 0 ? ) or one (for dps= ? 1 ? ) bcl clock after the selected time slot (tsdpxy.tss). note: stovxy and ackxy are useful for synchronizing microcontroller accesses and receive/transmit operations. one bcl clock is equivalent to two dcl clock cycles. 70 sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd (58)
peb 3081 pef 3081 detailed register description data sheet 161 2000-09-27 preliminary 4.3.12 asti - acknowledge synchronous transfer interrupt value after reset: 00 h for general information please refer to chapter 3.7.1.1 . ackxy ... acknowledge synchronous transfer interrupt after an stixy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ackxy bit to ? 1 ? . 4.3.13 msti - mask synchronous transfer interrupt value after reset: ff h for the msti register the following logical states are applied: 0: interrupt is not masked 1: interrupt is masked for general information please refer to chapter 3.7.1.1 . stovxy ... synchronous transfer overflow for stixy mask bits for the corresponding stovxy interrupt bits. stixy ... synchronous transfer interrupt xy mask bits for the corresponding stixy interrupt bits. 70 asti 0000ack 21 ack 20 ack 11 ack 10 wr (58) 70 msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd/wr (59)
peb 3081 pef 3081 detailed register description data sheet 162 2000-09-27 preliminary 4.3.14 sds_conf - configuration register for serial data strobes value after reset: 00 h for general information on sds1/2_bcl please refer to chapter 3.7.2 . diom_inv ... du/dd on iom timeslot inverted 0: du/dd are active during sds1 high phase and inactive during the low phase. 1: du/dd are active during sds1 low phase and inactive during the high phase. this bit has only effect if diom_sds is set to ? 1 ? otherwise diom_inv is don ? t care. diom_sds ... du/dd on iom controlled via sds1 0: the pin sds1 and its configuration settings are used for serial data strobe only. the iom-2 data lines are not affected. 1: the du/dd lines are deactivated during the high/low phase (selected via diom_inv) of the sds1 signal. the sds1 timeslot is selected in sds1_cr. sdsx_bcl ... enable iom bit clock for sdsx 0: the serial data strobe is generated in the programmed timeslot. 1: the iom bit clock is generated in the programmed timeslot. 70 sds_ conf 0000diom_ inv diom_ sds sds2_ bcl sds1_ bcl rd/wr (5a)
peb 3081 pef 3081 detailed register description data sheet 163 2000-09-27 preliminary 4.3.15 mcda - monitoring cda bits value after reset: ff h mcdaxy ... monitoring cdaxy bits bit 7 and bit 6 of the cdaxy registers are mapped into the mcda register. this can be used for monitoring the d-channel bits on du and dd and the ? echo bits ? on the tic bus with the same register 4.3.16 mor - monitor receive channel value after reset: ff h contains the monitor data received in the iom-2 monitor channel according to the monitor channel protocol. the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs. 4.3.17 mox - monitor transmit channel value after reset: ff h contains the monitor data to be transmitted in iom-2 monitor channel according to the monitor channel protocol.the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs 70 mcda mcda21 mcda20 mcda11 mcda10 rd (5b) bit7 bit6 bit7 bit6 bit7 bit6 bit7 bit6 70 mor monitor receiver data rd (5c) 70 mox monitor transmit data wr (5c)
peb 3081 pef 3081 detailed register description data sheet 164 2000-09-27 preliminary 4.3.18 mosr - monitor interrupt status register value after reset: 00 h mdr ... monitor channel data received mer ... monitor channel end of reception mda ... monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab ... monitor channel data abort 4.3.19 mocr - monitor control register value after reset: 00 h mre ... monitor receive interrupt enable 0: monitor interrupt status mdr generation is masked 1: monitor interrupt status mdr generation is enabled mrc ... mr bit control determines the value of the mr bit: 0: mr is always ? 1 ? . in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1: mr is internally controlled by the sbcx-x according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1). 70 mosr mdr mer mda mab 0 0 0 0 rd (5d) 70 mocr mre mrc mie mxc 0 0 0 0 rd/wr (5e)
peb 3081 pef 3081 detailed register description data sheet 165 2000-09-27 preliminary mie ... monitor interrupt enable monitor interrupt status mer, mda, mab generation is enabled (1) or masked (0). mxc ... mx bit control determines the value of the mx bit: 0: the mx bit is always ? 1 ? . 1: the mx bit is internally controlled by the sbcx-x according to monitor channel protocol. 4.3.20 msta - monitor status register value after reset: 00 h mac ... monitor transmit channel active the data transmisson in the monitor channel is in progress. tout ... time-out read-back value of the tout bit. 4.3.21 mconf - monitor configuration register value after reset: 00 h tout... time-out 0: the monitor time-out function is disabled 1: the monitor time-out function is enabled msta 00000mac0tout rd (5f) mconf0000000tout wr (5f)
peb 3081 pef 3081 detailed register description data sheet 166 2000-09-27 preliminary 4.4 interrupt and general configuration 4.4.1 ista - interrupt status register value after reset: 00 h for all interrupts in the ista register following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated st ... synchronous transfer this interrupt is generated to enable the microcontroller to lock on to the iom timing for synchronous transfers. the source can be read from the sti register. cic ... c/i channel change a change in c/i channel 0 or c/i channel 1 has been recognized. the actual value can be read from cir0 or cir1. aux ... auxiliary interrupts signals an interrupt generated from external awake (pin eaw ), watchdog timer overflow (wov) or from the timer (tin). the source can be read from the auxiliary interrupt register auxi. tran ... transceiver interrupt an interrupt originated in the transceiver interrupt status register (istatr) has been recognized. mos ... monitor status a change in the monitor status register (mosr) has occured. note: a read of the ista register clears none of the interrupts. they are only cleared by reading the corresponding status register. 70 ista 0 0 st cic aux tran mos 0 rd (60)
peb 3081 pef 3081 detailed register description data sheet 167 2000-09-27 preliminary 4.4.2 mask - mask register value after reset: ff h for the mask register following logical states are applied: 0: interrupt is enabled 1: interrupt is disabled each interrupt source in the ista register can selectively be masked/disabled by setting the corresponding bit in mask to ? 1 ? . masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to ? 0 ? . note: in the event of a c/i channel change, cic is set in ista even if the corresponding mask bit in mask is set, but no interrupt is generated. 4.4.3 auxi - auxiliary interrupt status register value after reset: 00 h for all interrupts in the ista register following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated eaw ... external awake interrupt an interrupt from the eaw pin has been detected. wov ... watchdog timer overflow signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits wtc1 and wtc2 (mode1 register) in the correct manner. a reset pulse has been generated by the sbcx-x. tin ... timer interrupt an interrupt originated from the timer is recognized, i.e the timer has expired. 70 mask 1 1 st cic aux tran mos 1 wr (60) 70 auxi 0 0 eaw wov tin 0 0 0 rd (61)
peb 3081 pef 3081 detailed register description data sheet 168 2000-09-27 preliminary 4.4.4 auxm - auxiliary mask register value after reset: ff h for the mask register following logical states are applied: 0: interrupt is enabled 1: interrupt is disabled each interrupt source in the auxi register can selectively be masked/disabled by setting the corresponding bit in auxm to ? 1 ? . masked interrupt status bits are not indicated when auxi is read. instead, they remain internally stored and pending, until the mask bit is reset to ? 0 ? . 4.4.5 mode1 - mode1 register value after reset: 00 h wtc1, 2 ... watchdog timer control 1, 2 after the watchdog timer mode has been selected (rss = ? 11 ? ) the watchdog timer is started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bit in the following sequence to reset and restart the watchdog timer. if wtc1/2 is not written fast enough in this way, the timer expires and a wov-interrupt (auxi register) together with a reset pulse is generated. 70 auxm 1 1 eaw wov tin 1 1 1 wr (61) 70 mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 rd/wr (62) wtc1 wtc2 1. 2. 1 0 0 1
peb 3081 pef 3081 detailed register description data sheet 169 2000-09-27 preliminary cfs ... configuration select this bit determines clock relations and recovery on s/t and iom interfaces. 0: the iom interface clock and frame signals are always active, "power down" state included. the states "power down" and "power up" are thus functionally identical except for the indication: pd = 1111 and pu = 0111. with the c/i command timing (tim) the microcontroller can enforce the "power up" state and with c/i command deactivation indication (di) the "power down" state is reached again. however, it is also possible to activate the s-interface directly with the c/i command activate request (ar 8/10/l) without the tim command. 1: the iom interface clock and frame signals are normally inactive ("power down"). for activating the iom-2 clocks the "power up" state can be induced by software (iom_cr.spu) or by resetting cfs again. after that the s-interface can be activated with the c/i command activate request (ar 8/10/l). the "power down" state can be reached again with the c/i command deactivation indication (di). note: after reset the iom interface is always active. to reach the "power down" state the cfs-bit has to be set. for general information please refer to chapter 3.3.8 . rss2, rss1... reset source selection 2,1 the sbcx-x reset sources for the rsto output pin can be selected according to the table below. rss c/i code change eaw watchdog timer bit 1 bit 0 0 0 -- -- -- 0 1 (reserved) 10 x x -- 11 -- -- x
peb 3081 pef 3081 detailed register description data sheet 170 2000-09-27 preliminary if rss = ? 00 ? no above listed reset source is selected and therefore no reset is generated at rsto . watchdog timer after the selection of the watchdog timer (rss = ? 11 ? ) the timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bits in two consecutive bit pattern (see description of the wtc1, 2 bits) otherwise the watchdog timer expires and a reset pulse of 125 s t 250 s is generated. deactivation of the watchdog timer is only possible with a hardware reset. if rss = ? 10 ? is selected the following two reset sources generate a reset pulse of 125 s t 250s at the rsto pin: - external (subscriber) awake (eaw ) the eaw input pin serves as a request signal from the subscriber to initiate the awake function in a terminal and generates a reset pulse (in te mode only). - exchange awake (c/i code) a c/i code change generates a reset pulse. after a reset pulse generated by the sbcx-x and the corresponding interrupt (wov or cic) the actual reset source can be read from the ista. 4.4.6 mode2 - mode2 register value after reset: 00 h int_pol ... interrupt polarity selects the polarity of the interrupt pin int . 0: low active with open drain characteristic (default) 1: high active with push pull characteristic ppsdx ... push/pull output for sdx (sci interface) 0: the sdx pin has open drain characteristic 1: the sdx pin has push/pull characteristic 70 mode20000int_ pol 0 0 ppsdx rd/wr (63)
peb 3081 pef 3081 detailed register description data sheet 171 2000-09-27 preliminary 4.4.7 id - identification register value after reset: 01 h design ... design number the design number allows to identify different hardware designs of the sbcx-x by software. 01 h : version 1.3 (all other codes reserved) 4.4.8 sres - software reset register value after reset: 00 h res_xx ... reset functional block xx a reset can be activated on the functional block c/i-handler, monitor channel, iom handler, s-transceiver and to pin rsto . setting one of these bits to ? 1 ? causes the corresponding block to be reset for a duration of 4 bcl clock cycles, except res_rsto which is activated for a duration of 125 ... 250s. the bits are automatically reset to ? 0 ? again. 70 id 0 0 design rd (64) 70 sres res_ ci 00res_ mon 0res_ iom res_ tr res_ rsto wr (64)
peb 3081 pef 3081 detailed register description data sheet 172 2000-09-27 preliminary 4.4.9 timr - timer register value after reset: 00 h tmd ... timer mode the timer can be used in two different modes of operation. 0: count down timer. an interrupt is generated only once after a time period of 1 ... 63 ms. 1: periodic timer. an interrupt is periodically generated every 1 ... 63 ms (see cnt). cnt ... timer counter 0: timer off. 1 ... 63: timer period = 1 ... 63 ms by writing ? 0 ? to cnt the timer is immediately stopped. a value different from that determines the time period after which an interrupt will be generated. if the timer is already started with a certain cnt value and is written again before an interrupt has been released, the timer will be reset to the new value and restarted again. an interrupt is indicated to the host in auxi.tin. note: reading back this value delivers back the current counter value which may differ from the programmed value if the counter is running. 70 timr tmd 0 cnt rd/wr (65)
peb 3081 pef 3081 electrical characteristics data sheet 173 2000-09-27 preliminary 5 electrical characteristics 5.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. the supply voltage must show a monotonic rise. parameter symbol limit values unit min. max. ambient temperature under bias peb pef t a 0 ? 45 +70 +85 c storage temperature t stg ? 55 150 c input/output voltage on any pin with respect to ground v s ? 0.3 5.25 v maximum voltage on any pin with respect to ground v max 5.5 v
peb 3081 pef 3081 electrical characteristics data sheet 174 2000-09-27 preliminary 5.2 dc characteristics v dd / v ss = 3.3v = 5 %; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. h-input level (except pins sr1/2) v ih 2.0 5.25 v l-input level (except pins sr1/2) v il ? 0.3 0.8 v h-output level (except pin xtal2, sx1/2) v oh 2.4 v i oh = - 400 a l-output level (except pin xtal2, sx1/2) v ol 0.45 v i ol = 6 ma (du, dd, c768) i ol = 4.5 ma (acl ) i ol = 2 ma (all others) input leakage current output leakage current (all pins except sx1/2,sr1/2,xtal1/2) i li i lo 1 1 a a 0v< v in peb 3081 pef 3081 electrical characteristics data sheet 175 2000-09-27 preliminary 5.3 capacitances t a = 25 c, v dd = 3.3v = 5 % v ssa = 0 v, v ss = 0 v, f c = 1 mhz, unmeasured pins grounded. parameter symbol limit values unit remarks min. max. input capacitance i/o capacitance c in c i/o 7 7 pf pf all pins except sx1,2 and xtal1,2 output capacitance against v ss c out 10 pf pins sx1,2
peb 3081 pef 3081 electrical characteristics data sheet 176 2000-09-27 preliminary 5.4 oscillator specification recommended oscillator circuits figure 67 oscillator circuits note: it is important to note that the load capacitance depends on the recommendation of the crystal specification. typical values are 22 ... 33 pf. xtal1 clock characteristics (external oscillator input) parameter symbol limit values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 40 pf oscillator mode fundamental parameter limit values min. max. duty cycle 1:2 2:1 its09659 7.68 mhz xtal1 xtal2 xtal2 xtal1 n.c. oscillator external signal crystal oscillator mode driving from external source 42 41 41 42 pf 33 33 pf c l l c
peb 3081 pef 3081 electrical characteristics data sheet 177 2000-09-27 preliminary 5.5 ac characteristics t a = 0 to 70 c, v dd = 3.3 v 5 % inputs are driven to 2.4 v for a logical "1" and to 0.45 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 68 . figure 68 input/output waveform for ac tests its09660 = 100 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf
peb 3081 pef 3081 electrical characteristics data sheet 178 2000-09-27 preliminary 5.6 iom-2 interface timing figure 69 iom-2 timing (te mode) itd09663 t fsd t iis iih t t iod bcd t bcd t sdd t fsc (o) dcl (o) du/dd (i) du/dd (o) sds (o) fsc/bcl (o)
peb 3081 pef 3081 electrical characteristics data sheet 179 2000-09-27 preliminary figure 70 iom-2 timing (lt-s, lt-t, nt mode) note: min. value in synchronous state, max. value in non-synchronous state. parameter symbol limit values unit min. max. iom output data delay t iod 60 ns iom input data setup t iis 4ns iom input data hold t iih 3ns fsc strobe delay (see note) t fsd -135 15 ns strobe signal delay t sdd 50 ns bcl delay t bcd 30 ns frame sync setup t fss 20 ns frame sync hold t fsh 30 ns frame sync width t fsw 40 ns t fss t fsh t fsw fsc (i) dcl (i) du/dd (i) iih t iis t du/dd (o) bit 0 bit 0 sdd t sds (o) t iod itt09680 t fss t fsh
peb 3081 pef 3081 electrical characteristics data sheet 180 2000-09-27 preliminary dcl clock output characteristics figure 71 definition of clock period and width dcl clock input characteristics symbol limit values unit test condition min. typ. max. t p 585 651 717 ns osc 100 ppm t wh 260 325 391 ns osc 100 ppm t wl 260 325 391 ns osc 100 ppm parameter limit values unit min. max. duty cycle 40 60 % 2.3 v
peb 3081 pef 3081 electrical characteristics data sheet 181 2000-09-27 preliminary 5.7 serial control interface (sci) timing figure 72 sci interface parameter sci interface symbol limit values unit min max scl cycle time t 1 200 ns scl high time t 2 = 100 ns scl low time t 3 = 100 ns cs setup time t 4 = 2ns cs hold time t 5 10 ns sdr setup time t 6 = 10 ns sdr hold time t 7 = 6ns sdx data out delay t 8 = 30 ns cs high to sdx tristate t 9 40 ns cs scl sdr sdx t 4 t 2 t 3 t 1 t 9 t 5 t 6 t 7 t 8
peb 3081 pef 3081 electrical characteristics data sheet 182 2000-09-27 preliminary 5.8 reset figure 73 reset signal res parameter symbol limit values unit test conditions min. length of active low state t res 4 ms power on/power down to power up (standby) 2 x dcl clock cycles during power up (standby) 21150_26 res t res
peb 3081 pef 3081 electrical characteristics data sheet 183 2000-09-27 preliminary 5.9 s-transceiver parameter symbol limit values unit test condition min. typ. max. v dd = 3.3v 5 %; v ss = 0v; t a = 0 to 70 c power supply current- power down - clocks off - clocks on i pd1 i pd2 300 3 a ma inputs at v ss / v dd no output loads except sx1,2 (50 ?) power supply current - s operational (96 khz) - b1=00 h ,b2=ff h , d=0 i op1 i op2 i op3 30 30 25 ma ma ma dcl=1536 khz dcl=4096 khz dcl=1536 khz absolute value of output pulse amplitude | vsx2 ? vsx1 | v x 1.17 v r l = transmitter output current i x 26 ma r l = 5.6 ? transmitter output impedance (sx1,2) z x 10 0 k ? ? inactive or during binary one; during binary zero r l = 50 ? receiver input impedance (sr1,2) z r 30 k ? v dd = 3.3 v
peb 3081 pef 3081 electrical characteristics data sheet 184 2000-09-27 preliminary 5.10 recommended transformer specification parameter symbol limit values unit test condition min. typ. max. transformer ratio 1:1 main inductance l 25 20 mh mh no dc current, 10 khz 2.5 ma dc current, 10 khz leakage inductance l l 8h10 khz capacitance between primary and secondary side c80pf1 khz copper resistance r 1.7 2.0 2.3 w
peb 3081 pef 3081 package outlines data sheet 185 2000-09-27 preliminary 6 package outlines p-mqfp-44 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our dimensions in mm smd = surface mounted device
peb 3081 pef 3081 package outlines data sheet 186 2000-09-27 preliminary sorts of packing package outlines for tubes, trays etc. are contained in our dimensions in mm smd = surface mounted device p-tqfp-48 (plastic thin quad flat package)
peb 3081 pef 3081 appendix data sheet 187 2000-09-27 preliminary 7 appendix transceiver, c/i-channel handler, auxiliary interface name76543210addrr/wres reserved 00 h - 21 h tr_ mode2 00000dim2dim1dim022 h r/w 00 h reserved 23-2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h tr_ conf0 dis_ tr bus en_ icv 0 l1sw 0 exlp ldd 30 h r/w 01h tr_ conf1 0rpll_ adj en_ sfsc 00xx x31 h r/w tr_ conf2 dis_ tx pds 0 rlp 0 0 sgp sgd 32 h r/w 80 h tr_sta rinf slip icv 0 fsyn 0 ld 33 h r00 h tr_cmd xinf dprio tddis pd lp_a 0 34 h r/w 08 h sqrr1 msyn mfen 0 0 sqr11sqr12sqr13sqr14 35 h r40 h sqxr1 0 mfen 0 0 sqx11sqx12sqx13 sqx14 35 h w4f h sqrr2 sqr21sqr22sqr23sqr24sqr31sqr32sqr33sqr34 36 h r00 h sqxr2 sqx21sqx22sqx23sqx24sqx31sqx32sqx33 sqx34 36 h w00 h sqrr3 sqr41sqr42sqr43sqr44sqr51sqr52sqr53sqr54 37 h r00 h sqxr3 sqx41sqx42sqx43sqx44sqx51sqx52sqx53 sqx54 37 h w00 h
peb 3081 pef 3081 appendix data sheet 188 2000-09-27 preliminary istatr 0 x x x ld ric sqc sqw 38 h r00 h masktr1111ldricsqcsqw39 h r/w ff h tr_ mode 0000 dch_ inh mode 2 mode 1 mode 0 3a h r/w 00 h reserved 3b h acfg100000od2od1od03c h r/w 00 h acfg20000aclled003d h r/w 00 h aoe 11111oe2oe1oe03e h r/w ff h arx -----ar2ar1ar03f h r atx 00000at2at1at03f h w00 h transceiver, c/i-channel handler, auxiliary interface name76543210addrr/wres
peb 3081 pef 3081 appendix data sheet 189 2000-09-27 preliminary iom handler (timeslot , data port selection, cda data and cda control register) name76543210addrr/wres cda10 controller data access register (ch10) 40 h r/w ff h cda11 controller data access register (ch11) 41 h r/w ff h cda20 controller data access register (ch20) 42 h r/w ff h cda21 controller data access register (ch21) 43 h r/w ff h cda_ tsdp10 dps 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 tss 47 h r/w 81 h reserved 48-4b h tr_ tsdp_ bc1 dps 0 0 tss 4c h r/w 00 h tr_ tsdp_ bc2 dps 0 0 tss 4dh r/w 01 h cda1_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4e h r/w 00 h cda2_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4f h r/w 00 h
peb 3081 pef 3081 appendix data sheet 190 2000-09-27 preliminary iom handler (control registers, synchronous transfer interrupt control), monitor handler name 76543210addrr/wres tr_cr (ci_cs=0) en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 50 h r/w f8 h trc_cr (ci_cs=1) 00000 cs2-0 50 h r/w 00 h reserved 51-52 h dci_cr (ci_cs=0) dps_ ci1 en_ ci1 00000053 h r/w 80 h dcic_cr (ci_cs=1) 00000 cs2-0 53 h r/w 00 h mon_cr dps en_ mon 000 cs2-0 54 h r/w 40 h sds1_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 55 h r/w 00 h sds2_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 56 h r/w 00 h iom_cr spu dis_ aw ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom 57 h r/w 08 h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0 0 0 0 ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h sds_ conf 0000diom_ inv diom_ sds sds2_ bcl sds1_ bcl 5a h r/w 00 h mcda mcda21 mcda20 mcda11 mcda10 5b h rff h
peb 3081 pef 3081 appendix data sheet 191 2000-09-27 preliminary mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosrmdrmermdamab00005d h r00 h mocrmremrcmiemxc00005e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h
peb 3081 pef 3081 appendix data sheet 192 2000-09-27 preliminary interrupt, general configuration registers name76543210addrr/wres ista 0 0 st cic aux tran mos 0 60 h r00 h mask 1 1 st cic aux tran mos 1 60 h wff h auxi 0 0 eaw wov tin 0 0 0 61 h r00 h auxm 1 1 eaw wov tin 1 1 1 61 h wff h mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 62 h r/w 00 h mode20000int_ pol 0 0 ppsdx 63 h r/w 00 h id 0 0 design 64 h r01 h sres res_ ci 00res_ mon 0res_ iom res_ tr res_ rsto 64 h w00 h timr tmd 0 cnt 65 h r/w 00 h reserved 66 h - 6f h
peb 3081 pef 3081 preliminary data sheet 193 2000-09-27 a absolute maximum ratings 173 ac characteristics 177 acfg1 register 147 acfg2 register 147 ackxy bits 161 acl bit 147 activation 79 activation indication - pin acl 37 activation led 37 activation/deactivation of iom-2 interface 119 aoe register 148 appendix 187 applications 18 ar2-0 bits 148 architecture 25 arx register 148 asti register 161 asynchronous awake 121 at2-0 bits 149 atx register 149 aux bit 166 auxi register 167 auxiliary interface 122 auxm register 168 b bac bit 134 bas bit 133 bus bit 135 c c/i channel 109 capacitances 175 cda_tsdpxy registers 151 cdax_cr register 152 cdaxy registers 150 cfs bit 168 ci_cs bit 158 ci1e bit 134 cic bit 166 cic1/0 bits 133 cicw bit 134 cir0 register 133 cir1 register 134 cix0 register 134 cix1 register 135 clkm bit 158 clock generation 55 cnt bits 172 codr0 bits 133 codr1 bits 134 codx0 bits 134 codx1 bits 135 control of layer-1 60 controller data access 87 d dc characteristics 174 dch_inh bit 145 d-channel access control intelligent nt 115 s-bus d-channel control in lt-t 115 s-bus priority mechanism 113 tic bus 111 dci_cr register 154 deactivation 79 delay between iom-2 and s 44 design bits 171 device architecture 25 dim2-0 bits 132 dis_aw bit 158 dis_iom bit 158 dis_od bit 158 dis_tr bit 135 dis_tx bit 137 dprio bit 140 dps bit 151, 156 dps_ci1 bit 154 e eaw bit 167 electrical characteristics 173 en_b2/1r bits 153
peb 3081 pef 3081 preliminary data sheet 194 2000-09-27 en_b2/1x bits 153 en_bcl bit 158 en_ci1 bit 154 en_d bit 153 en_i0 bit 152 en_i1 bit 152 en_icv bit 135 en_mon bit 156 en_o0 bit 152 en_o1 bit 152 en_sfsc bit 137 en_tbm bit 152 ens_tssx bits 157 exchange awake 34 exlp bit 135 external reset input 34 f features 15 fsyn bit 139 functional blocks 25 i i/o lines 122 icv bit 139 id register 171 int_pol bit 170 intelligent nt 115 interrupt structure 32 iom_cr register 158 iom-2 82 frame structure (lt) 84 frame structure (nt) 84 frame structure (te) 83 handler 85 interface timing 178 lt-s, lt-t, nt modes 82 monitor channel 99 te mode 82 ista register 166 istatr register 144 j jitter 58 l l1sw bit 135 ld bit 139, 144 ldd bit 135 led bit 147 led output 37 level detection 52 logic symbol 17 looping data 88 lp_a bit 140 lt-t mode 115 m mab bit 164 mac bit 165 mask register 167 masktr register 145 mcda register 163 mcdaxy bits 163 mconf register 165 mda bit 164 mdr bit 164 mer bit 164 mfen bit 141, 142 microcontroller interfaces 27 mie bit 164 mocr register 164 mode1 register 168 mode2 register 170 mode2-0 bits 145 mon_cr register 156 monitor channel error treatment 103 handshake procedure 100 interrupt logic 108 master device 105 slave device 106 time-out procedure 107 monitoring data 92
peb 3081 pef 3081 preliminary data sheet 195 2000-09-27 monitoring tic bus 92 mor register 163 mos bit 166 mosr register 164 mox register 163 mrc bit 164 mre bit 164 msta register 165 msti register 161 msyn bit 141 multiframing 42 mxc bit 164 o od2-0 bits 147 oe2-0 bits 148 oscillator 176 oscillator clock output 59 overview 12 p package outlines 185 pd bit 140 pds bit 137 pin configuration 19 ppsdx bit 170 r receive pll 58 register description 124 res_xxx bits 171 reset generation 33 reset source selection 33 reset timing 182 ric bit 144 rinf bits 139 rlp bit 137 rpll_adj bit 137 rss2/1 bits 168 s s/g bit 117, 133 s/t-interface 38 circuitry 49 coding 40 delay compensation 51 external protection circuitry 49 multiframing 42 receiver characteristics 48 transceiver enable/disable 52 transmitter characteristics 47 s-bus priority mechanism 113 sci - serial control interface 28 sci interface timing 181 sds 96 sds_conf register 162 sds2/1_bcl bits 162 sdsx_cr registers 157 serial data strobe 96 sgd bit 137 sgp bit 137 shifting data 88 slip bit 139 software reset 34 spu bit 158 sqc bit 144 sqr11-14 bits 141 sqr21-24 bits 142 sqr31-34 bits 142 sqr41-44 bits 143 sqr51-54 bits 143 sqrr1 register 141 sqrr2 register 142 sqrr3 register 143 sqw bit 144 sqx11-14 bits 142 sqx21-24 143 sqx31-34 bits 143 sqx41-44 bits 143 sqx51-54 bits 143 sqxr1 register 142 sqxr2 register 143 sqxr3 register 143 sres register 171 st bit 166 state machine
peb 3081 pef 3081 preliminary data sheet 196 2000-09-27 lt-s mode 69 nt mode 74 te and lt-t mode 62 sti register 160 stixy bits 160, 161 stop/go bit 117, 133 stovxy bits 160, 161 strobed data clock 96 subscriber awake 34 swap bit 152 synchronous transfer 93 t tba2-0 bits 134 tddis bit 140 test functions 53 tic bus 111 tic_dis bit 158 timer 35 timr register 172 tin bit 167 tmd bit 172 tout bit 165 tr_cmd register 140 tr_conf0 register 135 tr_conf1 register 137 tr_conf2 register 137 tr_cr register 153 tr_mode register 145 tr_mode2 register 132 tr_sta register 139 tr_tsdp_bc1/2 registers 151 tran bit 166 transceiver enable/disable 52 transformer specification 184 tss bits 151, 157 typical applications 18 w watchdog timer 34 wov bit 167 wtc1/2 bits 168 x xinf bits 140
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